1 | /*****************************************************
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2 | Date : 08.01.2024
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3 | Author : stefan h.
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4 | Chip type : ATtiny817 / ATtiny817 Xplained Mini
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5 | Program type : Application
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6 | Clock frequency : 20,000000 MHz
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7 | Data Stack size :
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8 | *****************************************************/
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9 | //------------------------------------- INCLUDE --------------------------------
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10 | #include <xc.h> // include processor files - each processor file is guarded.
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11 | #include <util/atomic.h>
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12 | #include <util/twi.h>
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13 |
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14 | //------------------------------------- DEFINES --------------------------------
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15 | #define TRUE 1
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16 | #define FALSE 0
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17 | #define INVALID -1
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18 | #define ON 1
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19 | #define OFF 0
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20 | #define START 1
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21 | #define STOP 0
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22 | #define SET 1
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23 | #define CLEAR 0
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24 | #define TOGGLE 1
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25 | #define BOOL signed char
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26 | #define CHAR char
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27 | #define U8 unsigned char
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28 | #define S8 signed char
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29 |
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30 | //-------------------------------------- FUSES ---------------------------------
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31 | // ATtiny817 Configuration Bit Settings
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32 |
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33 | FUSES = {
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34 | .WDTCFG = 0x08, // WDTCFG {PERIOD=1KCLK, WINDOW=OFF}
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35 | .BODCFG = 0xE5, // BODCFG {SLEEP=ENABLED, ACTIVE=ENABLED, SAMPFREQ=1KHz, LVL=BODLEVEL7}
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36 | .OSCCFG = 0x7E, // OSCCFG {FREQSEL=20MHZ, OSCLOCK=CLEAR}
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37 | .TCD0CFG = 0x00, // TCD0CFG {CMPA=CLEAR, CMPB=CLEAR, CMPC=CLEAR, CMPD=CLEAR, CMPAEN=CLEAR, CMPBEN=CLEAR, CMPCEN=CLEAR, CMPDEN=CLEAR}
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38 | .SYSCFG0 = 0xF6, // SYSCFG0 {EESAVE=CLEAR, RSTPINCFG=UPDI, CRCSRC=NOCRC}
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39 | .SYSCFG1 = 0xFF, // SYSCFG1 {SUT=64MS}
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40 | .APPEND = 0x00, // APPEND {APPEND=User range: 0x0 - 0xFF}
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41 | .BOOTEND = 0x00, // BOOTEND {BOOTEND=User range: 0x0 - 0xFF}
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42 | };
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43 |
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44 | LOCKBITS = 0xC5; // {LB=NOLOCK}
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45 |
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46 | //------------------------------------ PORTMUX ---------------------------------
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47 | /** PortMux
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48 | * alternate Pins of TWI0 to Pin A2 and A1
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49 | */
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50 | #define PORTMUX_CONFIG PORTMUX.CTRLB = (PORTMUX_TWI0_ALTERNATE_gc)
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51 |
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52 | //------------------------------------- PORT -----------------------------------
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53 | /** Port A Configuration Register
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54 | * PIN FUNCTION DDR PORT
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55 | * PIN7: DIAG input pull-up
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56 | * PIN6: NC input pull-up
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57 | * PIN5: NC input pull-up
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58 | * PIN4: NC input pull-up
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59 | * PIN3: NC input pull-up
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60 | * PIN2: TWI0 SCL input pull-up (TWI0 config overwrites)
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61 | * PIN1: TWI0 SDA input pull-up (TWI0 config overwrites)
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62 | * PIN0: RESET input pull-up
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63 | **/
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64 | #define PORTA_CONFIG PORTA.PIN7CTRL = (PORT_PULLUPEN_bm); \
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65 | PORTA.PIN6CTRL = (PORT_PULLUPEN_bm); \
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66 | PORTA.PIN5CTRL = (PORT_PULLUPEN_bm); \
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67 | PORTA.PIN4CTRL = (PORT_PULLUPEN_bm); \
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68 | PORTA.PIN3CTRL = (PORT_PULLUPEN_bm); \
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69 | PORTA.PIN2CTRL = (PORT_PULLUPEN_bm); \
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70 | PORTA.PIN1CTRL = (PORT_PULLUPEN_bm); \
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71 | PORTA.PIN0CTRL = (PORT_PULLUPEN_bm); \
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72 | PORTA.OUT = (0x00); \
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73 | PORTA.DIR = 0x00
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74 |
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75 | //------------------------------------ CLOCK -----------------------------------
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76 | /** Clock Configuration
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77 | * CLK_MAIN: 20MHz
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78 | * CLK_PER: 2MHz
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79 | **/
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80 | #define F_CPU 20000000UL
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81 | #define CLK_PER 2000000UL
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82 | #define UNLOCK_CCP CPU_CCP = CCP_IOREG_gc //System critical I/O register settings are protected from accidental modification. Changes to the protected I/O registers or bits, or execution of protected instructions, are only possible after the CPU writes a signature to the CCP register
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83 | #define CLKCTRL_PEN ((1<<CLKCTRL_PEN_bp)&CLKCTRL_PEN_bm)
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84 | #define CLKCTRL_PDIV CLKCTRL_PDIV_10X_gc
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85 | #define CLKCTRL_LOCKEN ((1<<CLKCTRL_LOCKEN_bp)&CLKCTRL_LOCKEN_bm)
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86 | #define CLK_CONFIG UNLOCK_CCP; CLKCTRL.MCLKCTRLB = (CLKCTRL_PDIV | CLKCTRL_PEN); UNLOCK_CCP; CLKCTRL.MCLKLOCK = CLKCTRL_LOCKEN; \
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87 | while (!(CLKCTRL.MCLKSTATUS&CLKCTRL_OSC32KS_bm) || !(CLKCTRL.MCLKSTATUS&CLKCTRL_OSC20MS_bm) || (CLKCTRL.MCLKSTATUS&CLKCTRL_SOSC_bm)){}
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88 |
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89 | //------------------------------------- WDT ------------------------------------
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90 | /** WDT Configuration
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91 | * Reset: 1K cycles (1.0s)
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92 | **/
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93 | #define WDT_RESET __asm("WDR")
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94 |
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95 | //------------------------------------ TWI -------------------------------------
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96 | #define SLAVE_ADDRESS 0x00
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97 | #define TWI_CONFIG TWI0.SCTRLA = (TWI_DIEN_bm | TWI_APIEN_bm | TWI_PIEN_bm | TWI_ENABLE_bm); TWI0.SADDR = SLAVE_ADDRESS
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98 | #define TWI_ADDRESS_MATCH_IF ((TWI0.SSTATUS & TWI_APIF_bm) && (TWI0.SSTATUS & TWI_AP_bm))
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99 | #define TWI_DATA_IF (TWI0.SSTATUS & TWI_DIF_bm)
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100 | #define TWI_STOP_IF ((TWI0.SSTATUS & TWI_APIF_bm) && (!(TWI0.SSTATUS & TWI_AP_bm)))
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101 | #define TWI_RXACK (!(TWI0.SSTATUS & TWI_RXACK_bm))
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102 | // Host wishes to read from client
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103 | #define TWI_MRST (TWI0.SSTATUS & TWI_DIR_bm)
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104 | //send ACK after receiving data / send requested data
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105 | #define TWI_ACK TWI0.SCTRLB = (TWI_ACKACT_ACK_gc | TWI_SCMD_RESPONSE_gc);
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106 | //send NACK after receiving data
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107 | #define TWI_NACK TWI0.SCTRLB = (TWI_ACKACT_NACK_gc | TWI_SCMD_COMPTRANS_gc);
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108 | //switch to the non adressed client mode...
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109 | #define TWI_RESET TWI0.SSTATUS |= (TWI_DIF_bm | TWI_APIF_bm); TWI0.SCTRLB = (TWI_SCMD_COMPTRANS_gc);
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110 |
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111 | #define TWI_MRST_SIZE 4
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112 | #define TWI_MTSR_SIZE 4
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113 | enum {
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114 | NO_TRANSACTION = 0,
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115 | MRST, //host receive, client transmit
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116 | MTSR //host transmit, client receive
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117 | };
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118 |
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119 |
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120 | //----------------------------------- VARIABLES --------------------------------
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121 | volatile U8 twi_mrst[TWI_MRST_SIZE];
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122 | volatile U8 twi_mtsr[TWI_MTSR_SIZE];
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123 | volatile U8 twi_transaction_mode = NO_TRANSACTION; //flag to know if other program parts can alter twi_mrst/twi_mtsr buffers
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124 | volatile U8 twi_received = FALSE; //flag for rx handler (e.g. update commands)
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125 | volatile U8 twi_transmitted = FALSE; //flag for tx handler (e.g. monitoring output)
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126 |
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127 | //------------------------------------ MAIN ------------------------------------
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128 |
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129 | void main_init(void) {
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130 | //disable global interrupt
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131 | cli();
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132 |
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133 | CLK_CONFIG;
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134 |
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135 | WDT_RESET;
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136 |
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137 | PORTMUX_CONFIG;
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138 |
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139 | PORTA_CONFIG;
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140 | // PORTB_CONFIG;
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141 | // PORTC_CONFIG;
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142 |
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143 | TWI_CONFIG;
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144 |
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145 | //enable global interrupts
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146 | sei();
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147 | }
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148 |
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149 | int main(void) {
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150 | main_init();
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151 |
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152 | while (1) {
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153 | WDT_RESET;
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154 | if (twi_received == TRUE) {
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155 | twi_received = FALSE;
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156 | if (twi_transaction_mode != MTSR) {
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157 | ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
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158 | //TODO: rx_handler
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159 | }
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160 | }
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161 | }
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162 | if (twi_transmitted == TRUE) {
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163 | twi_transmitted = FALSE;
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164 | if (twi_transaction_mode != MRST) {
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165 | ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
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166 | //TODO: tx_handler
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167 | }
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168 | }
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169 | }
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170 | }
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171 | }
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172 |
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173 | //-------------------------------------- ISR -----------------------------------
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174 | ISR(TWI0_TWIS_vect) {
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175 | static U8 mrst_cnt = 0;
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176 | static U8 mtsr_cnt = 0;
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177 |
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178 | static U8 isFirstByte = TRUE; // to bypass the NACK flag for the first byte in a transaction
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179 |
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180 | //TODO
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181 | // if (TWI0.SSTATUS & TWI_COLL_bm) {
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182 | // I2C_0_collision_callback();
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183 | // return;
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184 | // }
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185 | //
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186 | // if (TWI0.SSTATUS & TWI_BUSERR_bm) {
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187 | // I2C_0_bus_error_callback();
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188 | // return;
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189 | // }
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190 |
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191 | //ADDRESS
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192 | if (TWI_ADDRESS_MATCH_IF) {
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193 | if (TWI_MRST) {
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194 | twi_transaction_mode = MRST;
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195 | mrst_cnt = 0;
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196 | isFirstByte = TRUE;
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197 | } else {
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198 | twi_transaction_mode = MTSR;
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199 | mtsr_cnt = 0;
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200 | }
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201 | return;
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202 | }
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203 |
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204 | //DATA
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205 | if (TWI_DATA_IF) {
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206 | if (TWI_MRST) {
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207 | // Master wishes to read from slave
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208 | if (TWI_RXACK || isFirstByte) {
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209 | // Received ACK from master or First byte of transaction
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210 | isFirstByte = FALSE;
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211 | if (mrst_cnt >= TWI_MRST_SIZE) {
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212 | TWI0.SDATA = 0xFF;
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213 | } else {
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214 | TWI0.SDATA = twi_mrst[mrst_cnt];
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215 | mrst_cnt++;
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216 | }
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217 | TWI_ACK;
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218 | } else {
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219 | // Received NACK from master
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220 | TWI_RESET;
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221 | }
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222 | } else { // Master wishes to write to slave
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223 | twi_mtsr[mtsr_cnt] = TWI0.SDATA;
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224 | mtsr_cnt++;
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225 | if (mtsr_cnt > TWI_MTSR_SIZE) {
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226 | TWI_NACK;
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227 | } else {
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228 | TWI_ACK;
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229 | }
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230 | }
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231 | return;
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232 | }
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233 |
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234 | // STOP
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235 | if (TWI_STOP_IF) {
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236 | if (twi_transaction_mode == MRST) {
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237 | twi_transmitted = TRUE;
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238 | } else {
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239 | if (mtsr_cnt <= TWI_MTSR_SIZE) {
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240 | twi_received = TRUE;
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241 | }
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242 | }
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243 | twi_transaction_mode = NO_TRANSACTION;
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244 | TWI_RESET;
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245 | return;
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246 | }
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247 |
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248 | TWI_RESET;
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249 | }
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