Hallo,
habe ein kleines Programm geschrieben um Compare und Overflow zu testen.
Die Ports überwache ich mit einem Logic Analyzer (s.Bild).
Meine Frage ist nun, warum der OVF schon beim Start des Timers
ausgeführt wird.
1 | /* PA0 Taster
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2 | * Channel 0 PA1 Timer0 Start
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3 | * Channel 1 PA7 OC0B PWM
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4 | * Channel 2 PA2 TCNT0 Wert
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5 | * Channel 3 PA3 ISR Compare
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6 | * Channel 4 PA4 ISR OVF
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7 | */
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8 |
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9 | //-------------------------------------------------------------------------
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10 |
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11 | #define F_CPU 1000000UL // ATtiny44-20 with 1Mhz
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12 |
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13 | #define Timer0_stop TCCR0B &= ~((1<<CS00)|(1<<CS01)|(1<<CS02))
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14 | #define Timer0_start TCCR0B |= (1<<CS01)
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15 |
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16 | #include <avr/io.h>
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17 | #include <avr/interrupt.h>
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18 | #include <util/delay.h>
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19 |
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20 | //-------------------------------------------------------------------------
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21 |
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22 | ISR(TIM0_OVF_vect)
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23 | {
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24 | PORTA |= (1<<PA4);
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25 | _delay_us(100);
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26 | PORTA &= ~(1<<PA4);
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27 | }
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28 |
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29 | //-------------------------------------------------------------------------
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30 |
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31 | ISR(TIM0_COMPB_vect)
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32 | {
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33 | PORTA |= (1<<PA3);
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34 | }
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35 |
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36 | //-------------------------------------------------------------------------
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37 |
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38 | int main(void)
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39 | {
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40 | cli(); // clear Interrupt
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41 |
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42 | DDRA &= ~(1<<PA0); // PA0 Input
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43 | PORTA |= (1<<PA0); // Pullup on
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44 |
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45 | DDRA |= (1<<PA1)|(1<<PA2)|(1<<PA3)|(1<<PA4); // PA1 - PA4 Output
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46 | DDRA |= (1<<PA7); // PA7 OC0B
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47 | TCCR0A = (1<<COM0B1)|(1<<WGM00)|(1<<WGM01); // fast PWM
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48 | TCCR0B = (1<<WGM02); // fast PWM
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49 |
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50 | OCR0A = 250; // Top
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51 | OCR0B = 125; // Compare
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52 |
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53 | TIMSK0 = (1<<OCIE0B)|(1<<TOIE0); // Compare und OVF
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54 |
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55 | sei(); // set Interrupt
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56 |
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57 | //---------------------------------------------------------------------------
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58 |
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59 | while(1)
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60 |
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61 | {
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62 | if(!(PINA & (1<<PA0)))
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63 | {
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64 | _delay_ms(1000);
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65 | TCNT0 = 0;
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66 | PORTA |= (1<<PA1);
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67 | Timer0_start;
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68 | }
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69 |
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70 | if(TCNT0 == 125)
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71 | {
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72 | PORTA |= (1<<PA2);
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73 | }
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74 | }
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