Vorab: Test in der Konsole...
C:\Users\Privat>cargo --version
cargo 1.70.0 (ec8a8a0ca 2023-04-25)
C:\Users\Privat>
C:\Users\Privat>clang --version
clang version 16.0.0
Target: x86_64-pc-windows-msvc
Thread model: posix
InstalledDir: C:\Program Files\LLVM\bin
C:\Users\Privat>
=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+
So noch einmal versucht zu kompilieren:
C:\Users\Privat\Desktop\velvet-chess-5.2.1\velvet-chess-5.2.1>
C:\Users\Privat\Desktop\velvet-chess-5.2.1\velvet-chess-5.2.1>cargo build --release
Compiling fathomrs v1.0.0 (C:\Users\Privat\Desktop\velvet-chess-5.2.1\velvet-chess-5.2.1\fathomrs)
Compiling tch v0.11.0
Compiling torch-sys v0.11.0
The following warnings were emitted during compilation:
warning: fathom/src/tbprobe.c:196:9: warning: 'max' macro redefined [-Wmacro-redefined]
warning: #define max(a,b) a > b ? a : b
warning: ^
warning: C:\Program Files (x86)\Windows Kits\10\Include\10.0.22621.0\ucrt\stdlib.h:1282:17: note: previous definition is here
warning: #define max(a,b) (((a) > (b)) ? (a) : (b))
warning: ^
warning: fathom/src/tbprobe.c:197:9: warning: 'min' macro redefined [-Wmacro-redefined]
warning: #define min(a,b) a < b ? a : b
warning: ^
warning: C:\Program Files (x86)\Windows Kits\10\Include\10.0.22621.0\ucrt\stdlib.h:1283:17: note: previous definition is here
warning: #define min(a,b) (((a) < (b)) ? (a) : (b))
warning: ^
warning: fathom/src/tbprobe.c:2459:41: warning: comparison of integers of different signs: 'int' and 'unsigned int' [-Wsign-compare]
warning: if (popcount(pos->white | pos->black) <= cardinalityDTM) {
warning: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ^ ~~~~~~~~~~~~~~
warning: fathom/src/tbprobe.c:2459:7: error: always_inline function '_mm_popcnt_u64' requires target feature 'popcnt', but would be inlined into function 'tb_expand_mate' that is compiled without support for 'popcnt'
warning: if (popcount(pos->white | pos->black) <= cardinalityDTM) {
warning: ^
warning: fathom/src/tbprobe.c:125:38: note: expanded from macro 'popcount'
warning: #define popcount(x) (int)_mm_popcnt_u64((x))
warning: ^
warning: 3 warnings and 1 error generated.
error: failed to run custom build command for fathomrs v1.0.0 (C:\Users\Privat\Desktop\velvet-chess-5.2.1\velvet-chess-5.2.1\fathomrs)
Caused by:
process didn't exit successfully: C:\Users\Privat\Desktop\velvet-chess-5.2.1\velvet-chess-5.2.1\target\release\build\fathomrs-0f12ca6177a15b31\build-script-build (exit code: 1)
--- stdout
TARGET = Some("x86_64-pc-windows-msvc")
OPT_LEVEL = Some("3")
HOST = Some("x86_64-pc-windows-msvc")
cargo:rerun-if-env-changed=CFLAGS_x86_64-pc-windows-msvc
CFLAGS_x86_64-pc-windows-msvc = None
cargo:rerun-if-env-changed=CFLAGS_x86_64_pc_windows_msvc
CFLAGS_x86_64_pc_windows_msvc = None
cargo:rerun-if-env-changed=HOST_CFLAGS
HOST_CFLAGS = None
cargo:rerun-if-env-changed=CFLAGS
CFLAGS = None
cargo:rerun-if-env-changed=CRATE_CC_NO_DEFAULTS
CRATE_CC_NO_DEFAULTS = None
DEBUG = Some("false")
running: "clang" "-O3" "-ffunction-sections" "-fdata-sections" "--target=x86_64-pc-windows-msvc" "-static" "-I" "fathom/src" "-Wall" "-Wextra" "-D_CRT_SECURE_NO_WARNINGS" "-o" "C:\Users\Privat\Desktop\velvet-chess-5.2.1\velvet-chess-5.2.1\target\release\build\fathomrs-120535b6c197c6c9\out\fathom/src/tbprobe.o" "-c" "fathom/src/tbprobe.c"
cargo:warning=fathom/src/tbprobe.c:196:9: warning: 'max' macro redefined [-Wmacro-redefined]
cargo:warning=#define max(a,b) a > b ? a : b
cargo:warning= ^
cargo:warning=C:\Program Files (x86)\Windows Kits\10\Include\10.0.22621.0\ucrt\stdlib.h:1282:17: note: previous definition is here
cargo:warning= #define max(a,b) (((a) > (b)) ? (a) : (b))
cargo:warning= ^
cargo:warning=fathom/src/tbprobe.c:197:9: warning: 'min' macro redefined [-Wmacro-redefined]
cargo:warning=#define min(a,b) a < b ? a : b
cargo:warning= ^
cargo:warning=C:\Program Files (x86)\Windows Kits\10\Include\10.0.22621.0\ucrt\stdlib.h:1283:17: note: previous definition is here
cargo:warning= #define min(a,b) (((a) < (b)) ? (a) : (b))
cargo:warning= ^
cargo:warning=fathom/src/tbprobe.c:2459:41: warning: comparison of integers of different signs: 'int' and 'unsigned int' [-Wsign-compare]
cargo:warning= if (popcount(pos->white | pos->black) <= cardinalityDTM) {
cargo:warning= ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ^ ~~~~~~~~~~~~~~
cargo:warning=fathom/src/tbprobe.c:2459:7: error: always_inline function '_mm_popcnt_u64' requires target feature 'popcnt', but would be inlined into function 'tb_expand_mate' that is compiled without support for 'popcnt'
cargo:warning= if (popcount(pos->white | pos->black) <= cardinalityDTM) {
cargo:warning= ^
cargo:warning=fathom/src/tbprobe.c:125:38: note: expanded from macro 'popcount'
cargo:warning=#define popcount(x) (int)_mm_popcnt_u64((x))
cargo:warning= ^
cargo:warning=3 warnings and 1 error generated.
exit code: 1
--- stderr
error occurred: Command "clang" "-O3" "-ffunction-sections" "-fdata-sections" "--target=x86_64-pc-windows-msvc" "-static" "-I" "fathom/src" "-Wall" "-Wextra" "-D_CRT_SECURE_NO_WARNINGS" "-o" "C:\Users\Privat\Desktop\velvet-chess-5.2.1\velvet-chess-5.2.1\target\release\build\fathomrs-120535b6c197c6c9\out\fathom/src/tbprobe.o" "-c" "fathom/src/tbprobe.c" with args "clang" did not execute successfully (status code exit code: 1).
warning: build failed, waiting for other jobs to finish...
C:\Users\Privat\Desktop\velvet-chess-5.2.1\velvet-chess-5.2.1>rustc --print target-features
Features supported by rustc for this target:
adx - Support ADX instructions.
aes - Enable AES instructions.
avx - Enable AVX instructions.
avx2 - Enable AVX2 instructions.
avx512bf16 - Support bfloat16 floating point.
avx512bitalg - Enable AVX-512 Bit Algorithms.
avx512bw - Enable AVX-512 Byte and Word Instructions.
avx512cd - Enable AVX-512 Conflict Detection Instructions.
avx512dq - Enable AVX-512 Doubleword and Quadword Instructions.
avx512er - Enable AVX-512 Exponential and Reciprocal Instructions.
avx512f - Enable AVX-512 instructions.
avx512gfni - Enable Galois Field Arithmetic Instructions.
avx512ifma - Enable AVX-512 Integer Fused Multiple-Add.
avx512pf - Enable AVX-512 PreFetch Instructions.
avx512vaes - Promote selected AES instructions to AVX512/AVX registers.
avx512vbmi - Enable AVX-512 Vector Byte Manipulation Instructions.
avx512vbmi2 - Enable AVX-512 further Vector Byte Manipulation Instructions.
avx512vl - Enable AVX-512 Vector Length eXtensions.
avx512vnni - Enable AVX-512 Vector Neural Network Instructions.
avx512vp2intersect - Enable AVX-512 vp2intersect.
avx512vpclmulqdq - Enable vpclmulqdq instructions.
avx512vpopcntdq - Enable AVX-512 Population Count Instructions.
bmi1 - Support BMI instructions.
bmi2 - Support BMI2 instructions.
cmpxchg16b - 64-bit with cmpxchg16b (this is true for most x86-64 chips, but not the first AMD chips).
ermsb - REP MOVS/STOS are fast.
f16c - Support 16-bit floating point conversion instructions.
fma - Enable three-operand fused multiple-add.
fxsr - Support fxsave/fxrestore instructions.
gfni - Enable Galois Field Arithmetic Instructions.
lzcnt - Support LZCNT instruction.
movbe - Support MOVBE instruction.
pclmulqdq - Enable packed carry-less multiplication instructions.
popcnt - Support POPCNT instruction.
rdrand - Support RDRAND instruction.
rdseed - Support RDSEED instruction.
rtm - Support RTM instructions.
sha - Enable SHA instructions.
sse - Enable SSE instructions.
sse2 - Enable SSE2 instructions.
sse3 - Enable SSE3 instructions.
sse4.1 - Enable SSE 4.1 instructions.
sse4.2 - Enable SSE 4.2 instructions.
sse4a - Support SSE 4a instructions.
ssse3 - Enable SSSE3 instructions.
tbm - Enable TBM instructions.
vaes - Promote selected AES instructions to AVX512/AVX registers.
vpclmulqdq - Enable vpclmulqdq instructions.
xsave - Support xsave instructions.
xsavec - Support xsavec instructions.
xsaveopt - Support xsaveopt instructions.
xsaves - Support xsaves instructions.
crt-static - Enables C Run-time Libraries to be statically linked.
Code-generation features supported by LLVM for this target:
16bit-mode - 16-bit mode (i8086).
32bit-mode - 32-bit mode (80386).
3dnow - Enable 3DNow! instructions.
3dnowa - Enable 3DNow! Athlon instructions.
64bit - Support 64-bit instructions.
64bit-mode - 64-bit mode (x86_64).
allow-light-256-bit - Enable generation of 256-bit load/stores even if we prefer 128-bit.
amx-bf16 - Support AMX-BF16 instructions.
amx-fp16 - Support AMX amx-fp16 instructions.
amx-int8 - Support AMX-INT8 instructions.
amx-tile - Support AMX-TILE instructions.
avx512fp16 - Support 16-bit floating point.
avxifma - Enable AVX-IFMA.
avxneconvert - Support AVX-NE-CONVERT instructions.
avxvnni - Support AVX_VNNI encoding.
avxvnniint8 - Enable AVX-VNNI-INT8.
branchfusion - CMP/TEST can be fused with conditional branches.
cldemote - Enable Cache Line Demote.
clflushopt - Flush A Cache Line Optimized.
clwb - Cache Line Write Back.
clzero - Enable Cache Line Zero.
cmov - Enable conditional move instructions.
cmpccxadd - Support CMPCCXADD instructions.
crc32 - Enable SSE 4.2 CRC32 instruction (used when SSE4.2 is supported but function is GPR only).
cx8 - Support CMPXCHG8B instructions.
enqcmd - Has ENQCMD instructions.
false-deps-getmant - VGETMANTSS/SD/SH and VGETMANDPS/PD(memory version) has a false dependency on dest register.
false-deps-lzcnt-tzcnt - LZCNT/TZCNT have a false dependency on dest register.
false-deps-mulc - VF[C]MULCPH/SH has a false dependency on dest register.
false-deps-mullq - VPMULLQ has a false dependency on dest register.
false-deps-perm - VPERMD/Q/PS/PD has a false dependency on dest register.
false-deps-popcnt - POPCNT has a false dependency on dest register.
false-deps-range - VRANGEPD/PS/SD/SS has a false dependency on dest register.
fast-11bytenop - Target can quickly decode up to 11 byte NOPs.
fast-15bytenop - Target can quickly decode up to 15 byte NOPs.
fast-7bytenop - Target can quickly decode up to 7 byte NOPs.
fast-bextr - Indicates that the BEXTR instruction is implemented as a single uop with good throughput.
fast-gather - Indicates if gather is reasonably fast (this is true for Skylake client and all AVX-512 CPUs).
fast-hops - Prefer horizontal vector math instructions (haddp, phsub, etc.) over normal vector instructions with shuffles.
fast-lzcnt - LZCNT instructions are as fast as most simple integer ops.
fast-movbe - Prefer a movbe over a single-use load + bswap / single-use bswap + store.
fast-scalar-fsqrt - Scalar SQRT is fast (disable Newton-Raphson).
fast-scalar-shift-masks - Prefer a left/right scalar logical shift pair over a shift+and pair.
fast-shld-rotate - SHLD can be used as a faster rotate.
fast-variable-crosslane-shuffle - Cross-lane shuffles with variable masks are fast.
fast-variable-perlane-shuffle - Per-lane shuffles with variable masks are fast.
fast-vector-fsqrt - Vector SQRT is fast (disable Newton-Raphson).
fast-vector-shift-masks - Prefer a left/right vector logical shift pair over a shift+and pair.
fma4 - Enable four-operand fused multiple-add.
fsgsbase - Support FS/GS Base instructions.
fsrm - REP MOVSB of short lengths is faster.
harden-sls-ijmp - Harden against straight line speculation across indirect JMP instructions..
harden-sls-ret - Harden against straight line speculation across RET instructions..
hreset - Has hreset instruction.
idivl-to-divb - Use 8-bit divide for positive values less than 256.
idivq-to-divl - Use 32-bit divide for positive values less than 2^32.
invpcid - Invalidate Process-Context Identifier.
kl - Support Key Locker kl Instructions.
lea-sp - Use LEA for adjusting the stack pointer (this is an optimization for Intel Atom processors).
lea-uses-ag - LEA instruction needs inputs at AG stage.
lvi-cfi - Prevent indirect calls/branches from using a memory operand, and precede all indirect calls/branches from a register with an LFENCE instruction to serialize control flow. Also decompose RET instructions into a POP+LFENCE+JMP sequence..
lvi-load-hardening - Insert LFENCE instructions to prevent data speculatively injected into loads from being used maliciously..
lwp - Enable LWP instructions.
macrofusion - Various instructions can be fused with conditional branches.
mmx - Enable MMX instructions.
movdir64b - Support movdir64b instruction (direct store 64 bytes).
movdiri - Support movdiri instruction (direct store integer).
mwaitx - Enable MONITORX/MWAITX timer functionality.
nopl - Enable NOPL instruction (generally pentium pro+).
pad-short-functions - Pad short functions (to prevent a stall when returning too early).
pconfig - platform configuration instruction.
pku - Enable protection keys.
prefer-128-bit - Prefer 128-bit AVX instructions.
prefer-256-bit - Prefer 256-bit AVX instructions.
prefer-mask-registers - Prefer AVX512 mask registers over PTEST/MOVMSK.
prefetchi - Prefetch instruction with T0 or T1 Hint.
prefetchwt1 - Prefetch with Intent to Write and T1 Hint.
prfchw - Support PRFCHW instructions.
ptwrite - Support ptwrite instruction.
raoint - Support RAO-INT instructions.
rdpid - Support RDPID instructions.
rdpru - Support RDPRU instructions.
retpoline - Remove speculation of indirect branches from the generated code, either by avoiding them entirely or lowering them with a speculation blocking construct.
retpoline-external-thunk - When lowering an indirect call or branch using a retpoline, rely on the specified user provided thunk rather than emitting one ourselves. Only has effect when combined with some other retpoline feature.
retpoline-indirect-branches - Remove speculation of indirect branches from the generated code.
retpoline-indirect-calls - Remove speculation of indirect calls from the generated code.
sahf - Support LAHF and SAHF instructions in 64-bit mode.
sbb-dep-breaking - SBB with same register has no source dependency.
serialize - Has serialize instruction.
seses - Prevent speculative execution side channel timing attacks by inserting a speculation barrier before memory reads, memory writes, and conditional branches. Implies LVI Control Flow integrity..
sgx - Enable Software Guard Extensions.
shstk - Support CET Shadow-Stack instructions.
slow-3ops-lea - LEA instruction with 3 ops or certain registers is slow.
slow-incdec - INC and DEC instructions are slower than ADD and SUB.
slow-lea - LEA instruction with certain arguments is slow.
slow-pmaddwd - PMADDWD is slower than PMULLD.
slow-pmulld - PMULLD instruction is slow (compared to PMULLW/PMULHW and PMULUDQ).
slow-shld - SHLD instruction is slow.
slow-two-mem-ops - Two memory operand instructions are slow.
slow-unaligned-mem-16 - Slow unaligned 16-byte memory access.
slow-unaligned-mem-32 - Slow unaligned 32-byte memory access.
soft-float - Use software floating point features.
sse-unaligned-mem - Allow unaligned memory operands with SSE instructions (this may require setting a configuration bit in the processor).
tagged-globals - Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits..
tsxldtrk - Support TSXLDTRK instructions.
uintr - Has UINTR Instructions.
use-glm-div-sqrt-costs - Use Goldmont specific floating point div/sqrt costs.
use-slm-arith-costs - Use Silvermont specific arithmetic costs.
vzeroupper - Should insert vzeroupper instructions.
waitpkg - Wait and pause enhancements.
wbnoinvd - Write Back No Invalidate.
widekl - Support Key Locker wide Instructions.
x87 - Enable X87 float instructions.
xop - Enable XOP instructions.
Use +feature to enable a feature, or -feature to disable it.
For example, rustc -C target-cpu=mycpu -C target-feature=+feature1,-feature2
Code-generation features cannot be used in cfg or #[target_feature],
and may be renamed or removed in a future version of LLVM or rustc.
C:\Users\Privat\Desktop\velvet-chess-5.2.1\velvet-chess-5.2.1>
