Problem mit 8 Bit LFSR

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

​

​

entity lfsr is

port (

clk : in std_ulogic;

seed : in std_ulogic_vector(7 downto 0);

clear : in std_ulogic;

res : out std_ulogic_vector(7 downto 0)

);

end entity ; --lfsr

​

architecture lfsr_beh of lfsr is

signal current_state : std_ulogic_vector(7 downto 0);

signal next_state : std_ulogic_vector(7 downto 0);

signal feedback : std_ulogic;

​

begin

--Seed Assertion

​

--Reset Function

Shift_Reg : process (clk, clear)

begin

if (clear = '1') then

current_state <= seed;

elsif (clk = '1' and clk'event) then

current_state <= next_state;

end if;

end process;

​

--Loop

feedback <= current_state(7) xor current_state(3) xor current_state(0);

next_state <= feedback & current_state(7 downto 1);

res <= current_state;

​

end architecture ;

library ieee;

use ieee.std_logic_1164.all;

​

entity lfsr_tb is

end entity lfsr_tb;

​

architecture tb_arch of lfsr_tb is

-- Component declaration

component lfsr

port (

clk : in std_ulogic;

seed : in std_ulogic_vector(7 downto 0);

clear : in std_ulogic;

res : out std_ulogic_vector(7 downto 0)

);

end component;

​

-- Signal declarations

signal clk_tb : std_ulogic;

signal seed_tb : std_ulogic_vector(7 downto 0);

signal clear_tb : std_ulogic;

signal res_tb : std_ulogic_vector(7 downto 0);

​

begin

-- Component instantiation

DUT : lfsr

port map (

clk => clk_tb,

seed => seed_tb,

clear => clear_tb,

res => res_tb

);

​

-- Clock process

clk_process : process

begin

while now < 100 ns loop

clk_tb <= '0';

wait for 5 ns;

clk_tb <= '1';

wait for 5 ns;

end loop;

wait;

end process;

​

-- Stimulus process

stimulus_process : process

begin

seed_tb <= "00000001";

wait for 10 ns;

clear_tb <= '1'; -- Assert the clear signal

wait for 10 ns;

clear_tb <= '0'; -- Deassert the clear signal

for i in 0 To 4 loop

wait until clk_tb='1' and clk_tb'event;

end loop;

​

wait for 5 NS;

assert res_tb = X"F8" report "Failed Output";

report "Test Passed, output is correct";

wait for 10 ns;

​

end process;

​

end architecture tb_arch;