STM32WL kein Signal auf MISO-Leitung bei SUBGHZ SPI

 void SUBGHZSPI_DebugEnable(void) {

  RCC->AHB2ENR |= (1U << 0);    //enable GPIO-A

  GPIOA->MODER &= ~(3U << 8);    //reset PA4

  GPIOA->MODER |= (2U <<   8);    //set PA4

  GPIOA->MODER &= ~(3U << 10);  //reset PA5

  GPIOA->MODER |= (2U << 10);    //set PA5

  GPIOA->MODER &= ~(3U << 12);  //reset PA6

  GPIOA->MODER |= (2U << 12);    //set PA6

  GPIOA->MODER &= ~(3U << 14);  //reset PA7

  GPIOA->MODER |= (2U << 14);    //set PA7

  GPIOA->AFR[0] &= ~(15U<<16);  //reset AF of PA4

  GPIOA->AFR[0] |= (13U<<16);    //set AF13 of PA4

  GPIOA->AFR[0] &= ~(15U<<20);  //reset AF of PA5

  GPIOA->AFR[0] |= (13U<<20);    //set AF13 of PA5

  GPIOA->AFR[0] &= ~(15U<<24);  //reset AF of PA6

  GPIOA->AFR[0] |= (13U<<24);    //set AF13 of PA6

  GPIOA->AFR[0] &= ~(15U<<28);  //reset AF of PA7

  GPIOA->AFR[0] |= (13U<<28);    //set AF13 of PA7

  GPIOA->OSPEEDR |= (3U << 8);  //set output speed for PA4 to HIGH speed

  GPIOA->OSPEEDR |= (3U << 10);  //set output speed for PA5 to HIGH speed

  GPIOA->OSPEEDR |= (3U << 12);  //set output speed for PA6 to HIGH speed

  GPIOA->OSPEEDR |= (3U << 14);  //set output speed for PA7 to HIGH speed

}

void SUBGHZSPI_init(void) {

      RCC->APB3ENR |= (1<<0); // enable SUBGHZ SPI

      SUBGHZSPI->CR1 |= (1 << 9); // SSM

      SUBGHZSPI->CR1 |= (1 << 8); // SSI

      SUBGHZSPI->CR1 &= ~(7 << 3);

      SUBGHZSPI->CR1 |= (1<<3); // baudrate (1MHz)

      SUBGHZSPI->CR1 |= (1<<2); // Master

      SUBGHZSPI->CR1 &= ~(1<<10); // full-duplex

      SUBGHZSPI->CR2 |= (1<<12); // FIFO threshold 8bit

      SUBGHZSPI->CR1 |= (1<<6); // enable SPI

}

while(1) {

    PWR->SUBGHZSPICR &= ~(1 << 15); // NSS low

    while (!(SUBGHZSPI->SR & (1 << 1))); // TXE

    *(__IO uint8_t*)(&SUBGHZSPI->DR) = 0x13;

    while (!(SUBGHZSPI->SR & (1 << 0))); // RXNE

    uint32_t status = SUBGHZSPI->DR;

    PWR->SUBGHZSPICR |= (1 << 15); // NSS high

  }