Generics - Parameters

siehe Bücher/Links auf:

http://www.mikrocontroller.net/articles/Programmierbare_Logik

sorry falsches Fenster

generic map ist vhdl, in verilog macht man das wohl mit defparam.

Also beispiel die instanzierung eines brams in vhdl und v (aus xilinx 
Library guide):


vhdl:

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RAM16X1D_inst : RAM16X1D

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-- The following generic INIT declaration is only necessary

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-- if you wish to change the initial

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-- contents of the RAM to anything other than all zero's.

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generic map (

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  INIT: bit-vector := X"0000")

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port map (

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 DPO => DPO, -- Port A 1-bit data output

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 SPO => SPO, -- Port B 1-bit data output

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 A0 => A0, -- Port A address[0] input bit

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 A1 => A1, -- Port A address[1] input bit

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 A2 => A2, -- Port A address[2] input bit

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 A3 => A3, -- Port A address[3] input bit

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 D => D, -- Port A 1-bit data input

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 DPRA0 => DPRA0, -- Port B address[0] input bit

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 DPRA1 => DPRA1, -- Port B address[1] input bit

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 DPRA2 => DPRA2, -- Port B address[2] input bit

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 DPRA3 => DPRA3, -- Port B address[3] input bit

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 WCLK => WCLK, -- Port A write clock input

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 WE => WE -- Port A write enable input

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);

verilog:

RAM16X1D RAM16X1D_inst (
.DPO(DPO), // Port A 1-bit data output
.SPO(SPO), // Port B 1-bit data output
.A0(A0), // Port A address[0] input bit
.A1(A1), // Port A address[1] input bit
.A2(A2), // Port A address[2] input bit
.A3(A3), // Port A address[3] input bit
.D(D), // Port A 1-bit data input
.DPRA0(DPRA0), // Port B address[0] input bit
.DPRA1(DPRA1), // Port B address[1] input bit
.DPRA2(DPRA2), // Port B address[2] input bit
.DPRA3(DPRA3), // Port B address[3] input bit
.WCLK(WCLK), // Port A write clock input
.WE(WE) // Port A write enable input
);
// The following defparam INIT declaration is only necessary if you
// wish to change the initial contents of the RAM to anything other
// than all zero's. If the instance name for the RAM is is changes,
// that change needs to be reflected in the defparam statement.
defparam RAM16X1D_inst.INIT = 16'h0000;

Man beachte die zuweisung an INIT!

Ob man einem in verilog definierten parameter in vhdl einen wert 
zuweisen kann, ist mir unbekannt.