Hallo zusammen, habe mich an die Verarbeitung des ADC Signals gemacht. Gearbeitet wird mit dem LTC1407 wie er auch üblicherweise auf den XILINX TestBoard eingesetzt wird. Ich lege die SPI_MISO Daten in 2x14 I/Os, vom Prinzip her funktioniert die ganze Sache, nur habe ich das Problem das ich mit dem XC3S100E TQ144 arbeite. Für das Projekt benötige ich aber noch mehr I/Os - gibt es also eine Lösung die Daten intern zu speichern?
1 | library IEEE; |
2 | use IEEE.STD_LOGIC_1164.ALL; |
3 | use IEEE.STD_LOGIC_ARITH.ALL; |
4 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
5 | |
6 | entity adc_spi is |
7 | Port ( clk50 : in STD_LOGIC; |
8 | start_conv : in STD_LOGIC; |
9 | SPI_MISO : in std_logic; |
10 | CONV : out STD_LOGIC; |
11 | ADC1 : out std_logic_vector(13 downto 0) := (others => '0'); |
12 | ADC2 : out std_logic_vector(13 downto 0) := (others => '0'); |
13 | SCK : out STD_LOGIC); |
14 | end adc_spi; |
15 | |
16 | architecture Behavioral of adc_spi is |
17 | |
18 | type state_type is (IDLE, START,HI,LO,FINE); |
19 | signal next_state, state : state_type; |
20 | signal counter : integer range 0 to 35 :=0; |
21 | signal sample : std_logic; |
22 | begin
|
23 | |
24 | process(start_conv,state,counter) |
25 | |
26 | begin
|
27 | case state is |
28 | when IDLE => |
29 | if start_conv ='1' then |
30 | next_state <= START; |
31 | else
|
32 | next_state <= IDLE; |
33 | end if; |
34 | when START => |
35 | next_state <= HI; |
36 | when HI => |
37 | next_state <= LO; |
38 | when LO => |
39 | if counter = 34 then |
40 | next_state <= FINE; |
41 | else
|
42 | next_state <= HI; |
43 | end if; |
44 | when FINE => |
45 | next_state <= IDLE; |
46 | when others => |
47 | next_state <= IDLE; |
48 | end case; |
49 | |
50 | end process; |
51 | |
52 | process(clk50) |
53 | begin
|
54 | if clk50'event and clk50 ='1' then |
55 | state <= next_state; |
56 | end if; |
57 | end process; |
58 | |
59 | process (clk50) |
60 | variable index1 : integer range 0 to 15; |
61 | variable index2 : integer range 0 to 15; |
62 | begin
|
63 | |
64 | if clk50'event and clk50 ='1' then |
65 | |
66 | case state is |
67 | when IDLE => |
68 | SCK <= '0'; |
69 | CONV <= '0'; |
70 | sample <='0'; |
71 | when START => |
72 | SCK <= '0'; |
73 | CONV <= '1'; |
74 | counter <= 0; |
75 | sample <='0'; |
76 | index1 := 13; |
77 | index2 := 13; |
78 | when HI => |
79 | SCK <= '1'; |
80 | CONV <= '0'; |
81 | counter <= counter +1; |
82 | sample <='0'; |
83 | when LO => |
84 | SCK <= '0'; |
85 | CONV <= '0'; |
86 | |
87 | if(counter >2 and counter < 17) then |
88 | if index1 = 13 then |
89 | ADC1(index1) <= not SPI_MISO; |
90 | else
|
91 | ADC1(index1) <= SPI_MISO; |
92 | end if; |
93 | index1 := index1 -1; |
94 | sample <='1'; |
95 | elsif(counter > 18 and counter < 33) then |
96 | if index2 = 13 then |
97 | ADC2(index2) <= not SPI_MISO; |
98 | else
|
99 | ADC2(index2) <= SPI_MISO; |
100 | end if; |
101 | index2 := index2 -1; |
102 | sample <='1'; |
103 | else
|
104 | sample <='0'; |
105 | end if; |
106 | when FINE => |
107 | counter <= 0; |
108 | sample <='0'; |
109 | SCK <= '0'; |
110 | CONV <= '0'; |
111 | when others => |
112 | SCK <= '0'; |
113 | CONV <= '0'; |
114 | end case; |
115 | end if; |
116 | end process; |
117 | end Behavioral; |