RAM mit write_enable und read_enable

Habe versucht ein RAM mit write_enable und read_enable zu modellieren.
Mein Ansatz ist anscheinend falsch, da sich ISE Webpack standhaft 
weigert das entsprechende Schema zu öffnen. Eine Synthese ist jedoch 
möglich.
Die Language Schemas sind bekannt. Bitte keine Pauschalantworten wie: 
Geht nicht oder Think in Hardware.

Danke für eure Hilfe


entity ram is
   generic
   (
      address_width_ram   : integer := 8;
      data_width_ram   : integer := 8
   );

   port
   (
     clock_ram  : in  std_logic;
     data_in_ram   : in  std_logic_vector(0 to data_width_ram - 1);
     data_out_ram  : out std_logic_vector(0 to data_width_ram - 1);
     write_enable_ram  : in  std_logic;
     write_address_ram : in  std_logic_vector(0 to address_width_ram - 
1)
     read_enable_ram   : in   std_logic;
     read_address_ram  : in  std_logic_vector(0 to address_width_ram - 
1)
   );
end ram;

architecture ram_rtl of ram is
   type ram_type is array(0 TO ((2 ** address_width_ram) - 1)) of 
std_logic_vector(0 to data_width_ram - 1);
   signal ram : ram_type;
begin
  read_write : process (clock_ram)
  begin
    if rising_edge(clock_ram)
    then
      if write_enable_ram = '1' and read_enable_ram = '0'
      then
  -- Write to the RAM
  ram(to_integer(unsigned(write_address_ram))) <= data_in_ram;
      elsif read_enable_ram = '1' and write_enable_ram = '0'
      then
  -- Read from RAM
  data_out_ram <= ram(to_integer(unsigned(read_address_ram)));
      else
  null;
      end if;
    end if;
end process;
end architecture ram_rtl;