Hallo, ich hab da ein Problem und verstehe den Code nicht. Mein Aufgabe ist es ein RAM für ein Altera Board zu schreiben´. Nun hab ich auf der Altera Site ein Bsp RAM gefunden was eigentlich funktionieren sollte. Mein Problem ist ich verstehe folgende Zeile nicht.
1 | ARCHITECTURE rtl OF ram IS |
2 | TYPE RAM IS ARRAY(0 TO 2 ** ADDRESS_WIDTH - 1) OF std_logic_vector(DATA_WIDTH - 1 DOWNTO 0); |
Danke für jegliche Hilfe. Gruß Daniel
1 | LIBRARY ieee; |
2 | USE ieee.std_logic_1164.ALL; |
3 | USE ieee.numeric_std.ALL; |
4 | |
5 | ENTITY ram IS |
6 | GENERIC
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7 | (
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8 | ADDRESS_WIDTH : integer := 4; |
9 | DATA_WIDTH : integer := 8 |
10 | );
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11 | PORT
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12 | (
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13 | clock : IN std_logic; -- Takt |
14 | data : IN std_logic_vector(DATA_WIDTH - 1 DOWNTO 0); -- 8-bit data input to RAM |
15 | write_address : IN std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0); -- 4-bit read address input |
16 | read_address : IN std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0); -- 4-bit write address input |
17 | we : IN std_logic; -- Write enable input |
18 | q : OUT std_logic_vector(DATA_WIDTH - 1 DOWNTO 0) -- 8-bit data output of RAM |
19 | );
|
20 | END ram; |
21 | |
22 | ARCHITECTURE rtl OF ram IS |
23 | TYPE RAM IS ARRAY(0 TO 2 ** ADDRESS_WIDTH - 1) OF std_logic_vector(DATA_WIDTH - 1 DOWNTO 0); |
24 | |
25 | SIGNAL ram_block : RAM; |
26 | BEGIN
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27 | PROCESS (clock) |
28 | BEGIN
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29 | IF (clock'event AND clock = '1') THEN |
30 | IF (we = '1') THEN |
31 | ram_block(to_integer(unsigned(write_address))) <= data; |
32 | END IF; |
33 | |
34 | q <= ram_block(to_integer(unsigned(read_address))); |
35 | END IF; |
36 | END PROCESS; |
37 | END rtl; |