SRAM reagiert nicht

Hallo zusammen,

ich versuche ein SRAM auf einem Spartan 3 Eval. board anzusprechen. Nur 
leider gelingt es mir nicht, dem SRAM eine Antwort zu entlocken. In der 
Simulation sieht es OK aus. Anbei einen kleinen Demo Code, der 8 Bytes 
Schreibt, und danach wieder einliest.


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity memorytest is
port (         clk   : in    STD_LOGIC;
            sram_adr : out   STD_LOGIC_VECTOR (17 downto 0);
           sram_1_io : inout STD_LOGIC_VECTOR (15 downto 0);
        sram_1_o  : out   STD_LOGIC_VECTOR (15 downto 0);
           sram_2_io : inout STD_LOGIC_VECTOR (15 downto 0);
             sram_oe : out   STD_LOGIC;
             sram_we : out   STD_LOGIC;
           sram_1_ce : out   STD_LOGIC;
           sram_1_ub : out   STD_LOGIC;
           sram_1_lb : out   STD_LOGIC;
           sram_2_ce : out   STD_LOGIC;
           sram_2_ub : out   STD_LOGIC;
           sram_2_lb : out   STD_LOGIC);

end memorytest;

architecture Behavioral of memorytest is

signal counter: std_logic_vector ( 4 downto 0) :="00000";

begin

process (clk) begin
  if rising_edge (clk) then
    counter <= counter + 1;
  end if;
end process;

sram_1_ce <= '0';  -- chip 1 enable (low aktiv)
sram_1_ub <= '0';  -- oberes Byte enable (low aktiv)
sram_1_lb <= '0';  -- oberes Byte enable (low aktiv)

sram_2_ce <= '1';
sram_2_ub <= '1'; -- chip 2 disable
sram_2_lb <= '1';


process (clk) begin
  if rising_edge (clk) then
    sram_adr <= "000000000000000" & counter ( 3 downto 1);
    sram_oe  <=  not counter(4);  -- outout enable (low aktiv)
   sram_we  <=  not counter(4) and counter (0);
  end if;
end process;

process (clk) begin
  if rising_edge (clk) then
    if counter(4) = '0' then
       sram_1_io <= "0000000000000" & counter (3 downto 1);
    else
        sram_1_io <= (others => 'Z');
    end if;
  end if;
end process;

sram_1_o <= sram_1_io;

end Behavioral;