1 | Started : "Fit".
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2 | CS: block property: block_name=/HC573/EXPANDED_FlattenFull/HC573/my_latch<6>1 prop_name=TYPE prop_terse=XDM_PROPERTY_STRING "TYPE" "INV"
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3 |
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4 | CS: block property: block_name=/HC573/EXPANDED_FlattenFull/HC573 prop_name=TYPE prop_terse=XDM_PROPERTY_STRING "TYPE" "HC573"
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5 |
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6 |
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7 | Process "Fit" failed
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Irgenwie kann ich überhaupt nicht erkenne was das Problem sein soll,
Synthese geht ohne Probleme durch, Code:
1 | ----------------------------------------------------------------------------------
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2 | -- Create Date: 12:53:59 12/15/2009
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3 | -- Module Name: HC573 - Behavioral
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4 | ----------------------------------------------------------------------------------
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5 | library IEEE;
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6 | use IEEE.STD_LOGIC_1164.ALL;
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7 | use IEEE.STD_LOGIC_ARITH.ALL;
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8 | use IEEE.STD_LOGIC_UNSIGNED.ALL;
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9 |
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10 | entity HC573 is
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11 | Port ( addr_in : in STD_LOGIC_VECTOR (6 downto 0);
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12 | addr_out : out STD_LOGIC_VECTOR (6 downto 0);
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13 | latch : in STD_LOGIC
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14 | );
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15 | end HC573;
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16 |
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17 | architecture Behavioral of HC573 is
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18 | signal my_latch : std_logic_vector(6 downto 0);
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19 | begin
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20 | my_latch <= addr_in when latch = '1' else "1010101";
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21 | addr_out <= my_latch;
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22 | end Behavioral;
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