Hallo zusammen, ich baue gerade an einem Modul um mehrere 74HC595 zu bespielen. Jedoch verstehe ich nicht. WARUM das : led1DS<= PIN_RAMDAT(bitcounter-1); nicht geht. Ich habe das Modul stark abgespeckt um das Prinzip zu testen. Jedoch ohne Erfolg. Warum geht es nicht, hat jemand einen Ansatz? Danke ------------ CODE --------- entity ic74hc595 is Generic ( Laenge : integer := 8; -- Anzahl der zu übertragenden Bits Module : integer := 10 -- N-1 Module ); port( PIN_CLKIN : in std_logic; PIN_RESET : in std_logic; PIN_RAMADR : out std_logic_vector(7 downto 0); PIN_RAMDAT : in std_logic_vector(7 downto 0); -- Dateneingang PIN_RAMRD : out std_logic; -- ----------------------------------------------------------------- -- ZEILEN PIN_ZeilenCLKOUT : out std_logic; PIN_ZeilenDATAOUT : out std_logic; PIN_ZeilenLATCH : out std_logic; -- ----------------------------------------------------------------- -- Farben PIN_LedCLK : out std_logic; PIN_Led1DOUT : out std_logic; PIN_Led2DOUT : out std_logic; PIN_LedLATCH : out std_logic; PIN_LedOE : out std_logic ); end ic74hc595; ------------------------------------------------------------------------ --------- -- Architecture ----------------------------------------------------------------- ------------------------------------------------------------------------ --------- architecture Behavioral of ic74hc595 is -- Deklarationen ------------------------------------------------------------- ------------------------------------------------------------------------ ------ type tra_states is (ramReadH, ramReadL, reset_state, start_state, dataout_state, clkh_state, clkl_state, modulinc_state, modulCheck_state, latch_state, stop_state, latchen_state); signal tra_state : tra_states := reset_state; signal tra_byte_reg : std_logic_vector(7 downto 0); -- Transmitt byte signal zeilenShift : std_logic_vector(7 downto 0); signal zeilen_reg : std_logic_vector(7 downto 0); signal zeilenCLK : std_logic; signal zeilenDS : std_logic; signal zeilenLA : std_logic; signal ledCLK : std_logic; signal led1DS : std_logic; signal led2DS : std_logic; signal ledLA : std_logic; signal ledOE : std_logic; signal ramADR : std_logic_vector(7 downto 0) := (others => '0'); signal ramRD : std_logic; signal bitcounter : integer range 0 to Laenge; -- wenn bitcounter = Laenge --> alle Bits uebertragen signal modulcounter : integer range 0 to Module; ------------------------------------------------------------------------ ------ begin ------------------------------------------------------------------------ ------ Transmitter : process(PIN_CLKIN,PIN_RESET) begin if(PIN_RESET='1')then tra_state<=reset_state; elsif rising_edge(PIN_CLKIN) then case tra_state is -- --------------------------------------------------------------- -- Reset State -- --------------------------------------------------------------- -- Zurücksetzen aller Werte -- --------------------------------------------------------------- when reset_state => tra_state<= ramReadH; zeilen_reg <= "00000001"; ramRD <='0'; modulcounter<=0; ramADR<= (others => '0'); bitcounter <= Laenge; -- --------------------------------------------------------------- -- RAM ReadH/L -- --------------------------------------------------------------- -- Lesen des Wertes an der Adresse ramADR -- --------------------------------------------------------------- when ramReadH => ramRD<='1'; tra_state<= ramReadL; when ramReadL => ramRD<='0'; ramADR<=ramADR+1; tra_state<= start_state; -- --------------------------------------------------------------- -- start State -- --------------------------------------------------------------- -- Zurücksetzen der Einspeiswerte -- --------------------------------------------------------------- when start_state => bitcounter <= Laenge; tra_byte_reg <= PIN_RAMDAT(7 downto 0); tra_state <= dataout_state; when dataout_state => -------------------------------------------------------------- -- LEDS ledCLK<='0'; ledLA<='0'; zeilenCLK<='0'; zeilenLA<='0'; led2DS<='0'; led1DS<= PIN_RAMDAT(bitcounter-1); -------------------------------------------------------------- -- Zeilen if(modulcounter+1=Module) then zeilenDS<=zeilen_reg(bitcounter-1); end if; tra_state <= clkh_state; -- --------------------------------------------------------------- -- CLK High -- --------------------------------------------------------------- when clkh_state => ledCLK<='1'; tra_state <= clkl_state; bitcounter<=bitcounter-1; -------------------------------------------------------------- -- Zeilen if(modulcounter+1=Module) then zeilenCLK<='1'; end if; -- --------------------------------------------------------------- -- CLK LOW -- --------------------------------------------------------------- when clkl_state => ledCLK<='0'; zeilenCLK <='0'; if(bitcounter=0) then tra_state<= modulinc_state; else tra_state<= clkh_state; end if; -------------------------------------------------------------- -- Zeilen if(modulcounter+1=Module) then zeilenCLK<='0'; end if; -- --------------------------------------------------------------- -- ModulInc -- --------------------------------------------------------------- when modulinc_state => null; when others => null; end case; end if; end process; PIN_RAMADR <= ramADR; PIN_RAMRD <= ramRD; PIN_ZeilenCLKOUT <= zeilenCLK; PIN_ZeilenDATAOUT <= zeilenDS; PIN_ZeilenLATCH <= zeilenLA; PIN_LedCLK <= ledCLK; PIN_Led1DOUT <= led1DS; PIN_Led2DOUT <= led2DS; PIN_LedLATCH <= ledLA; PIN_LedOE <= ledOE; end Behavioral;
Thread beobachten
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