I2C-Core von Lattice (RD1005)

[Thomas (Gast)]

Hi Zusammen,

ich möchte den I2C-Core RD1005 von Lattice in Betrieb nehmen.
Dazu habe ich eine übergeordnete Zustandsmaschine erstellt, die den Core 
anregen soll. Leider bleiben SCL und SDA immer auf low.
Normale dachte ich, dass

Hat jemand Erfahrungen mit dem Core? Oder hat mir jemand von euch 
sonstige Tipps?
Ein Dankeschön im Voraus!!!




Die übergeordnete Statemachine:
______________________________________________________________________ 
__
-------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if
--instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity main is
    Port (
        SCL_PIN: out STD_LOGIC;
        SDA_PIN: inout STD_LOGIC;
        btn_RST: in STD_LOGIC;
        SysClk: in STD_LOGIC  --Systemtakt
        );
end main;

architecture Behavioral of main is

-----------------------------------------------------
--Component Declarations
----------------------------------------------------
component I2C_Top is
  port (
     SDA        : inout std_logic;
       SCL        : inout std_logic;
       Clock      : in std_logic;
       Reset_L    : in std_logic;
       CS_L       : in std_logic;
       A0         : in std_logic;
       A1         : in std_logic;
       A2         : in std_logic;
       RW_L       : in std_logic;
       INTR_L     : out std_logic;
       DATA       : inout std_logic_vector(7 downto 0)
   );
end component;


component ack_gen is
port(
    clk   : in std_logic;
      rst_l : in std_logic;
      cs_l  : in std_logic;
      ack_l : out std_logic);
end component;



----------------------------------------------------
--Constant Declarations
----------------------------------------------------
constant n: integer:=8;
--constant reset_i2c_l:     STD_LOGIC:='1';
constant stBitCnt:integer :=3;
-----------------------------------------------------
--Signal Declarations
-----------------------------------------------------

--main state machine

signal   m_state: std_logic_vector(stBitCnt-1 downto 0);--
signal ack_l: std_logic;

signal CS_L       :  std_logic;
signal Address :std_logic_vector(2 downto 0);
signal RW_L       :  std_logic;
signal INTR_L     :  std_logic;
signal DATA_OUT       :  std_logic_vector(7 downto 0);
signal Reset_L :std_logic;

signal scl :std_logic;
signal sda : std_logic;
signal data:std_logic_vector(7 downto 0);
constant  stIdle     :std_logic_vector(stBitCnt-1 downto 0):= "000";
constant  stStartWr  :std_logic_vector(stBitCnt-1 downto 0):= "001";
constant  stWaitAck  :std_logic_vector(stBitCnt-1 downto 0):= "010";
constant  stSetCS   :std_logic_vector(stBitCnt-1 downto 0):= "011";
constant  stStopWr   :std_logic_vector(stBitCnt-1 downto 0):= "100";

constant  stStartRd  :std_logic_vector(stBitCnt-1 downto 0):= "111";

------------------------------------------------
-- Procedures
------------------------------------------------


-------------------------------------------------
-- Module Implementation
------------------------------------------------

begin
Reset_L <= not btn_rst;

i2c_controller: I2C_Top
    Port map(
      SDA => SDA,
       SCL   => SCL,
       Clock => SysClk,
       Reset_L  => btn_RST,
       CS_L => CS_L,
       A0 => Address(0),
       A1 => Address(1),
       A2 => Address(2),
       RW_L => RW_L,
       INTR_L => INTR_L,
       DATA => DATA_OUT
   );

acknowledge_gen:    ack_gen
Port map(     clk =>SysClk,
      rst_l => btn_RST,
      cs_l => cs_l,
      ack_l => ack_l);



  ----------------------------------------------
  --state machine
  ----------------------------------------------

  --addr_bus <= "00";
--  EEPROM_addr_PIN <= addr_bus;
--  data_IO<=data_out when (i2c_rd_wr_l='0') else "ZZZZZZZZ";

   process(SysClk, btn_RST)
  begin
        if(btn_RST='1') then
           m_state <=stIdle;--- after 1 ns;
        elsif(SysClk' event and SysClk='1') then
          case m_state is
             when stIdle =>
              m_state <=stStartWr after 1 ns;

              when stStartWr =>
              --report "Writing Word Address";
              Address <= "000" ;
              RW_L <= '0';
              data_out <= "01010101";
              m_state <=stSetCS;

           when stSetCS =>
              cs_l     <= '0';
              m_state <= stWaitAck;

           when stWaitAck =>
              if (ack_l = '0') then
                cs_l <='1';
                m_state <=stStopWr;
              end if;

           when stStopWr =>
              --  i2c_cs_l <='1';
                RW_L     <= '1';
                data_out <="ZZZZZZZZ";
                m_state <=stStartRd;
           when stStartRd =>

          m_state <= stStartWr;
            --m_state <=stIdle after 1 ns;
           when  others =>
            m_state <=stIdle after 1 ns;
        end case;
      end if;
   end process;


  scl_pin<='Z' when scl='1' else '0';
 sda_pin<= 'Z' when sda='1' else '0';

--------------------------------------
-- tri-state buffer for data bus

data <= DATA_OUT when RW_L = '0' else "ZZZZZZZZ";
--------------------------------------
end Behavioral;




















______________________________________________________________________ 
__

[SuperWilly (Gast)]

Hast du das schon simuliert ?

[Thomas (Gast)]

Hi,

ja, mit dem selben Ergebnis, dass SCL und SDA dauerhaft auf low bleiben!