VHDL - Bus Deklaration - wofür?

Das ist ein eher exotisches feature das in der praxis nicht/kaum benutzt 
wird bzw nicht benötigt wird.

Zitat Ashenden:
If all of the drivers of a resolved signal are disconnected, the 
question of
the resulting signal value arises. There are two possibilities, 
depending on whether the signal was declared with signal kind register 
or bus. For register kind signals, the most recently determined value 
remains on the signal. This can be used to model charge storage nodes in 
MOS logic families. For bus kind signals, the resolution function must 
determine the value for the signal when no drivers are contributing to 
it. This is how tristate, open-collector and open-drain buses would 
typically be modeled.
Zitat ende.

Du bekommst es wieder weg indem du das betreffende Signal (nicht den 
Port) doppelklickst und Kind wieder auf None stellst.