Signale in Generate - [gelöst]

[Matthias K. (kruessi80)]

Hi,
habe gerade dass Problem, dass innerhalb des "generate" Signale
konstant werden und dann von der Synthese entfernt werden.

ps_gen : for I in 1 to C_MAX_PARTICIPANT generate
   constant C_MAX_PARTDATA : natural := 6;
   signal readVal_r : natural range 0 to C_MAX_PARTDATA-1;

   constant c_minVal : natural range 0 to C_MAX_PARTDATA * C_MAX_PARTICIPANT := (I-1)*6;
   constant c_maxVal : natural range 0 to C_MAX_PARTDATA * C_MAX_PARTICIPANT := I*6;
begin
   
   p_read: process (rst_n, clk)
   begin
      if (rst_n = '0') then
         readVal_r <= 0;
      elsif (clk_25'event and clk_25 = '1') then
         if (Enable = '1') then
            if (((Value > c_minVal) or (Value = c_minVal)) and ((Value < c_maxVal) or (Value = c_maxVal))) then
               readVal_r <= natural(Value-c_minVal);
            else
               readVal_r <= 0;
            end if;
         else
            readVal_r <= 0;
         end if;
      end if;
   end process;
   
   ps: partStat
   generic map (
      C_COUNT_WIDTH => C_COUNT_WIDTH)
   port map (
      rst_n          => rst_n,
      clk_25         => clk_25,
      value          => readVal_r
      ..)
end generate;

Bei der Synthese erhalte ich diese Meldungen.

INFO:Xst:2679 - Register <readVal_r0> in unit <statistic> has a constant value of 000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <readVal_r1> in unit <statistic> has a constant value of 000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <readVal_r2> in unit <statistic> has a constant value of 000 during circuit operation. The register is replaced by logic.

Leider kann ich mir dies nicht erklären.
Habt Ihr eine Idee?

Matthias

[edit]
Ich habe versehentlich das Eingangssignal "Value" mit

Value  : in natural range 0 to 2

deklariert, was natürlich falsch ist.
Korrekt ist:

Value  : in natural range 0 to 6*C_MAX_PARTICIPANT