Ich habe folgenden output eines counters in chipscope. Warum sieht der so komisch aus?
1 | library IEEE; |
2 | use IEEE.STD_LOGIC_1164.all; |
3 | use IEEE.STD_LOGIC_ARITH.all; |
4 | use IEEE.STD_LOGIC_UNSIGNED.all; |
5 | |
6 | entity doedel is |
7 | port ( |
8 | CLK1_FB : in std_logic; |
9 | -- deleted
|
10 | );
|
11 | end doedel ; |
12 | |
13 | architecture a of doedel is |
14 | |
15 | signal counter : std_logic_vector(15 downto 0); |
16 | |
17 | |
18 | begin
|
19 | |
20 | registers : process (CLK1_FB, RESETl) |
21 | begin
|
22 | if RESETl = '0' then |
23 | counter <= (others => '0'); |
24 | |
25 | elsif CLK1_FB = '1' and CLK1_FB'event then |
26 | |
27 | --counter <= std_logic_vector(unsigned(counter) + 1);
|
28 | counter <= counter + 1; |
29 | end if; |
30 | end process; |
31 | end a; |
Kann das ein Abtastproblem durch die chipscope clock sein? Eigentlich müssten doch die counter bits alternierend ca 50%:50% sein und nicht nur peeks. ???