1 | AT91PS_SPI pSPI = AT91C_BASE_SPI;
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2 | AT91PS_PIO pPIOA = AT91C_BASE_PIOA;
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3 | AT91PS_PMC pPMC = AT91C_BASE_PMC;
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4 | // not used: AT91PS_PDC pPDC_SPI = AT91C_BASE_PDC_SPI;
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5 |
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6 | // disable PIO from controlling MOSI, MISO, SCK (=hand over to SPI)
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7 | // keep CS untouched - used as GPIO pin during init
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8 | pPIOA->PIO_PDR = AT91C_PA12_MISO | AT91C_PA13_MOSI | AT91C_PA14_SPCK; // | NCPS_PDR_BIT;
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9 | // set pin-functions in PIO Controller
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10 | pPIOA->PIO_ASR = AT91C_PA12_MISO | AT91C_PA13_MOSI | AT91C_PA14_SPCK; /// not here: | NCPS_ASR_BIT;
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11 | /// not here: pPIOA->PIO_BSR = NPCS_BSR_BIT;
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12 |
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13 | // set chip-select as output high (unselect card)
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14 | pPIOA->PIO_PER = NCPS_PDR_BIT; // enable GPIO of CS-pin
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15 | pPIOA->PIO_SODR = NCPS_PDR_BIT; // set high
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16 | pPIOA->PIO_OER = NCPS_PDR_BIT; // output enable
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17 |
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18 | // enable peripheral clock for SPI ( PID Bit 5 )
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19 | pPMC->PMC_PCER = ( (euint32) 1 << AT91C_ID_SPI ); // n.b. IDs are just bit-numbers
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20 |
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21 | // SPI enable and reset
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22 | pSPI->SPI_CR = AT91C_SPI_SPIEN | AT91C_SPI_SWRST;
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23 |
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24 | #ifdef FIXED_PERIPH
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25 | // SPI mode: master, fixed periph. sel., FDIV=0, fault detection disabled
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26 | pSPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_PS_FIXED | AT91C_SPI_MODFDIS;
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27 | // set PCS for fixed select
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28 | // pSPI->SPI_MR &= 0xFFF0FFFF; // clear old PCS - redundant (AT91lib)
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29 | pSPI->SPI_MR |= ( (SPI_MR_PCS<<16) & AT91C_SPI_PCS ); // set PCS
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30 | #else
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31 | // SPI mode: master, variable periph. sel., FDIV=0, fault detection disabled
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32 | // Chip-Select-Decoder Mode (write state of CS-Lines in TDR)
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33 | pSPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCSDEC ;
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34 | #endif
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35 |
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36 | // set chip-select-register
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37 | // 8 bits per transfer, CPOL=1, ClockPhase=0, DLYBCT = 0
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38 | // TODO: Why has CPOL to be active here and non-active on LPC2000?
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39 | // Take closer look on timing diagrams in datasheets.
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40 | // not working pSPI->SPI_CSR[SPI_CSR_NUM] = AT91C_SPI_CPOL | AT91C_SPI_BITS_8 | AT91C_SPI_NCPHA;
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41 | // not working pSPI->SPI_CSR[SPI_CSR_NUM] = AT91C_SPI_BITS_8 | AT91C_SPI_NCPHA;
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42 | pSPI->SPI_CSR[SPI_CSR_NUM] = AT91C_SPI_CPOL | AT91C_SPI_BITS_8;
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43 | // not working pSPI->SPI_CSR[SPI_CSR_NUM] = AT91C_SPI_BITS_8;
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44 |
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45 | // slow during init
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46 | if_spiSetSpeed(0xFE);
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47 |
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48 | // enable
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49 | pSPI->SPI_CR = AT91C_SPI_SPIEN;
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50 |
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51 | /* Send 20 spi commands with card not selected */
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52 | for(i=0;i<21;i++) {
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53 | if_spiSend(iface,0xFF);
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54 | }
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55 |
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56 | /* enable automatic chip-select */
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57 | // reset PIO-registers of CS-pin to default
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58 | pPIOA->PIO_ODR = NCPS_PDR_BIT; // input
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59 | pPIOA->PIO_CODR = NCPS_PDR_BIT; // clear
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60 | // disable PIO from controlling the CS pin (=hand over to SPI)
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61 | pPIOA->PIO_PDR = NCPS_PDR_BIT;
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62 | // set pin-functions in PIO Controller (function NCPS for CS-pin)
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63 | pPIOA->PIO_ASR = NCPS_ASR_BIT;
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64 | pPIOA->PIO_BSR = NPCS_BSR_BIT;
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