1 | -- TestBench Template
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2 |
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3 | LIBRARY ieee;
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4 | USE ieee.std_logic_1164.ALL;
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5 | USE ieee.numeric_std.ALL;
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6 | use std.textio.all;
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7 | use ieee.std_logic_textio.all;
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8 |
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9 | ENTITY testbench IS
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10 | END testbench;
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11 |
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12 | ARCHITECTURE behavior OF testbench IS
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13 |
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14 | -- Component Declaration
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15 | COMPONENT FFT_1
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16 | PORT (
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17 | clk : IN STD_LOGIC;
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18 | start : IN STD_LOGIC;
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19 | xn_re : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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20 | xn_im : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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21 | fwd_inv : IN STD_LOGIC;
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22 | fwd_inv_we : IN STD_LOGIC;
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23 | scale_sch : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
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24 | scale_sch_we : IN STD_LOGIC;
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25 | rfd : OUT STD_LOGIC;
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26 | xn_index : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
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27 | busy : OUT STD_LOGIC;
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28 | edone : OUT STD_LOGIC;
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29 | done : OUT STD_LOGIC;
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30 | dv : OUT STD_LOGIC;
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31 | xk_index : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
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32 | xk_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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33 | xk_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
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34 | );
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35 | END COMPONENT;
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36 |
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37 | signal s_clk : STD_LOGIC := '1';
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38 | signal s_xn_re : STD_LOGIC_VECTOR(15 DOWNTO 0) := (others => '0');
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39 | signal s_xn_index : STD_LOGIC_VECTOR(9 DOWNTO 0) := (others => '0');
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40 | signal s_xk_re : STD_LOGIC_VECTOR(15 DOWNTO 0) := (others => '0');
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41 | signal s_xk_im : STD_LOGIC_VECTOR(15 DOWNTO 0) := (others => '0');
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42 |
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43 | FILE test_out_data: TEXT open WRITE_MODE is "E:\Doblinger\FFT\output_iFFT_tb.txt";
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44 |
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45 |
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46 | BEGIN
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47 |
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48 | s_clk <= not s_clk after 10 ns;
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49 |
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50 | -- Component Instantiation
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51 | uut : FFT_1
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52 | PORT MAP (
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53 | clk => s_clk,
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54 | start => '1',
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55 | xn_re => s_xn_re,
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56 | xn_im => "0000000000000000",
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57 | fwd_inv => '0',
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58 | fwd_inv_we => '1',
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59 | scale_sch => "000001010",
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60 | scale_sch_we => '1',
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61 | rfd => open,
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62 | xn_index => s_xn_index,
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63 | busy => open,
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64 | edone => open,
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65 | done => open,
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66 | dv => open,
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67 | xk_index => open,
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68 | xk_re => s_xk_re,
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69 | xk_im => s_xk_im
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70 | );
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71 |
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72 | tb : PROCESS
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73 | variable L1 : LINE;
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74 | BEGIN
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75 | --if s_clk 'event and s_clk = '1' then
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76 | wait for 2 ns;
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77 | write(L1, s_xk_re);
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78 | writeline(test_out_data, L1);
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79 | if s_xn_index = "0000000000" then
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80 | s_xn_re <= "0010000000000000";
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81 | else
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82 | s_xn_re <= "0000000000000000";
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83 | end if;
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84 | --end if;
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85 | END PROCESS tb;
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86 | --End Test Bench
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87 |
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88 | END;
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