von
Holger (Gast)
07.07.2014 16:25
Hallo kennt sich einer mit dem EFB Config für den MachXo2 Chip aus ?
Ich kopple den internen Clock Generator an den I2C-Bus.Unit#1.
IP-Express erzeugt nur einen I2C-Bus als Slave, aber ich will einen
Master.
Mein Ref-Design poste ich noch nach.
Damit aus dem MachXo2 Hardened Core auch ein I2C-Bus Signal rauskommt,
muss man die Struktur der BlackBox kennen.
Augenmerk gilt auch für den internen Oscillator, der muss laufen,sonst
geht der WishBone-Bus nicht, und das I2C-Bus Interface is tristate.
1 module efb (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i,
2 wb_dat_i, wb_dat_o, wb_ack_o, spi_clk, spi_miso, spi_mosi, spi_scsn,
3 spi_csn, ufm_sn, wbc_ufm_irq)/* synthesis NGD_DRC_MASK=1 */;
4 input wire wb_clk_i;
5 input wire wb_rst_i;
6 input wire wb_cyc_i;
7 input wire wb_stb_i;
8 input wire wb_we_i;
9 input wire [7:0] wb_adr_i;
10 input wire [7:0] wb_dat_i;
11 input wire spi_scsn;
12 input wire ufm_sn;
13 output wire [7:0] wb_dat_o;
14 output wire wb_ack_o;
15 output wire [0:0] spi_csn;
16 output wire wbc_ufm_irq;
17 inout wire spi_clk;
18 inout wire spi_miso;
19 inout wire spi_mosi;
20
21 wire spi_mosi_oe;
22 wire spi_mosi_o;
23 wire spi_miso_oe;
24 wire spi_miso_o;
25 wire spi_clk_oe;
26 wire spi_clk_o;
27 wire spi_mosi_i;
28 wire spi_miso_i;
29 wire spi_clk_i;
30 wire scuba_vlo;
31
32 BB BBspi_mosi (.I(spi_mosi_o), .T(spi_mosi_oe), .O(spi_mosi_i), .B(spi_mosi));
33
34 BB BBspi_miso (.I(spi_miso_o), .T(spi_miso_oe), .O(spi_miso_i), .B(spi_miso));
35
36 BB BBspi_clk (.I(spi_clk_o), .T(spi_clk_oe), .O(spi_clk_i), .B(spi_clk));
37
38 VLO scuba_vlo_inst (.Z(scuba_vlo));
39
40 defparam EFBInst_0.UFM_INIT_FILE_FORMAT = "HEX" ;
41 defparam EFBInst_0.UFM_INIT_FILE_NAME = "NONE" ;
42 defparam EFBInst_0.UFM_INIT_ALL_ZEROS = "ENABLED" ;
43 defparam EFBInst_0.UFM_INIT_START_PAGE = 2026 ;
44 defparam EFBInst_0.UFM_INIT_PAGES = 20 ;
45 defparam EFBInst_0.DEV_DENSITY = "7000L" ;
46 defparam EFBInst_0.EFB_UFM = "ENABLED" ;
47 defparam EFBInst_0.TC_ICAPTURE = "DISABLED" ;
48 defparam EFBInst_0.TC_OVERFLOW = "DISABLED" ;
49 defparam EFBInst_0.TC_ICR_INT = "OFF" ;
50 defparam EFBInst_0.TC_OCR_INT = "OFF" ;
51 defparam EFBInst_0.TC_OV_INT = "OFF" ;
52 defparam EFBInst_0.TC_TOP_SEL = "OFF" ;
53 defparam EFBInst_0.TC_RESETN = "ENABLED" ;
54 defparam EFBInst_0.TC_OC_MODE = "TOGGLE" ;
55 defparam EFBInst_0.TC_OCR_SET = 32767 ;
56 defparam EFBInst_0.TC_TOP_SET = 65535 ;
57 defparam EFBInst_0.GSR = "ENABLED" ;
58 defparam EFBInst_0.TC_CCLK_SEL = 1 ;
59 defparam EFBInst_0.TC_MODE = "CTCM" ;
60 defparam EFBInst_0.TC_SCLK_SEL = "PCLOCK" ;
61 defparam EFBInst_0.EFB_TC_PORTMODE = "WB" ;
62 defparam EFBInst_0.EFB_TC = "DISABLED" ;
63 defparam EFBInst_0.SPI_WAKEUP = "DISABLED" ;
64 defparam EFBInst_0.SPI_INTR_RXOVR = "DISABLED" ;
65 defparam EFBInst_0.SPI_INTR_TXOVR = "DISABLED" ;
66 defparam EFBInst_0.SPI_INTR_RXRDY = "DISABLED" ;
67 defparam EFBInst_0.SPI_INTR_TXRDY = "DISABLED" ;
68 defparam EFBInst_0.SPI_SLAVE_HANDSHAKE = "DISABLED" ;
69 defparam EFBInst_0.SPI_PHASE_ADJ = "DISABLED" ;
70 defparam EFBInst_0.SPI_CLK_INV = "DISABLED" ;
71 defparam EFBInst_0.SPI_LSB_FIRST = "DISABLED" ;
72 defparam EFBInst_0.SPI_CLK_DIVIDER = 3 ;
73 defparam EFBInst_0.SPI_MODE = "BOTH" ;
74 defparam EFBInst_0.EFB_SPI = "ENABLED" ;
75 defparam EFBInst_0.I2C2_WAKEUP = "DISABLED" ;
76 defparam EFBInst_0.I2C2_GEN_CALL = "DISABLED" ;
77 defparam EFBInst_0.I2C2_CLK_DIVIDER = 1 ;
78 defparam EFBInst_0.I2C2_BUS_PERF = "100kHz" ;
79 defparam EFBInst_0.I2C2_SLAVE_ADDR = "0b1000010" ;
80 defparam EFBInst_0.I2C2_ADDRESSING = "7BIT" ;
81 defparam EFBInst_0.EFB_I2C2 = "DISABLED" ;
82 defparam EFBInst_0.I2C1_WAKEUP = "DISABLED" ;
83 defparam EFBInst_0.I2C1_GEN_CALL = "DISABLED" ;
84 defparam EFBInst_0.I2C1_CLK_DIVIDER = 1 ;
85 defparam EFBInst_0.I2C1_BUS_PERF = "100kHz" ;
86 defparam EFBInst_0.I2C1_SLAVE_ADDR = "0b1000001" ;
87 defparam EFBInst_0.I2C1_ADDRESSING = "7BIT" ;
88 defparam EFBInst_0.EFB_I2C1 = "DISABLED" ;
89 defparam EFBInst_0.EFB_WB_CLK_FREQ = "40.0" ;
90 EFB EFBInst_0 (.WBCLKI(wb_clk_i), .WBRSTI(wb_rst_i), .WBCYCI(wb_cyc_i),
91 .WBSTBI(wb_stb_i), .WBWEI(wb_we_i), .WBADRI7(wb_adr_i[7]), .WBADRI6(wb_adr_i[6]),
92 .WBADRI5(wb_adr_i[5]), .WBADRI4(wb_adr_i[4]), .WBADRI3(wb_adr_i[3]),
93 .WBADRI2(wb_adr_i[2]), .WBADRI1(wb_adr_i[1]), .WBADRI0(wb_adr_i[0]),
94 .WBDATI7(wb_dat_i[7]), .WBDATI6(wb_dat_i[6]), .WBDATI5(wb_dat_i[5]),
95 .WBDATI4(wb_dat_i[4]), .WBDATI3(wb_dat_i[3]), .WBDATI2(wb_dat_i[2]),
96 .WBDATI1(wb_dat_i[1]), .WBDATI0(wb_dat_i[0]), .PLL0DATI7(scuba_vlo),
97 .PLL0DATI6(scuba_vlo), .PLL0DATI5(scuba_vlo), .PLL0DATI4(scuba_vlo),
98 .PLL0DATI3(scuba_vlo), .PLL0DATI2(scuba_vlo), .PLL0DATI1(scuba_vlo),
99 .PLL0DATI0(scuba_vlo), .PLL0ACKI(scuba_vlo), .PLL1DATI7(scuba_vlo),
100 .PLL1DATI6(scuba_vlo), .PLL1DATI5(scuba_vlo), .PLL1DATI4(scuba_vlo),
101 .PLL1DATI3(scuba_vlo), .PLL1DATI2(scuba_vlo), .PLL1DATI1(scuba_vlo),
102 .PLL1DATI0(scuba_vlo), .PLL1ACKI(scuba_vlo), .I2C1SCLI(scuba_vlo),
103 .I2C1SDAI(scuba_vlo), .I2C2SCLI(scuba_vlo), .I2C2SDAI(scuba_vlo),
104 .SPISCKI(spi_clk_i), .SPIMISOI(spi_miso_i), .SPIMOSII(spi_mosi_i),
105 .SPISCSN(spi_scsn), .TCCLKI(scuba_vlo), .TCRSTN(scuba_vlo), .TCIC(scuba_vlo),
106 .UFMSN(ufm_sn), .WBDATO7(wb_dat_o[7]), .WBDATO6(wb_dat_o[6]), .WBDATO5(wb_dat_o[5]),
107 .WBDATO4(wb_dat_o[4]), .WBDATO3(wb_dat_o[3]), .WBDATO2(wb_dat_o[2]),
108 .WBDATO1(wb_dat_o[1]), .WBDATO0(wb_dat_o[0]), .WBACKO(wb_ack_o),
109 .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), .PLL1STBO(), .PLLWEO(), .PLLADRO4(),
110 .PLLADRO3(), .PLLADRO2(), .PLLADRO1(), .PLLADRO0(), .PLLDATO7(),
111 .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(), .PLLDATO2(),
112 .PLLDATO1(), .PLLDATO0(), .I2C1SCLO(), .I2C1SCLOEN(), .I2C1SDAO(),
113 .I2C1SDAOEN(), .I2C2SCLO(), .I2C2SCLOEN(), .I2C2SDAO(), .I2C2SDAOEN(),
114 .I2C1IRQO(), .I2C2IRQO(), .SPISCKO(spi_clk_o), .SPISCKEN(spi_clk_oe),
115 .SPIMISOO(spi_miso_o), .SPIMISOEN(spi_miso_oe), .SPIMOSIO(spi_mosi_o),
116 .SPIMOSIEN(spi_mosi_oe), .SPIMCSN7(), .SPIMCSN6(), .SPIMCSN5(),
117 .SPIMCSN4(), .SPIMCSN3(), .SPIMCSN2(), .SPIMCSN1(), .SPIMCSN0(spi_csn[0]),
118 .SPICSNEN(), .SPIIRQO(), .TCINT(), .TCOC(), .WBCUFMIRQ(wbc_ufm_irq),
119 .CFGWAKE(), .CFGSTDBY());
120
121
122
123 // exemplar begin
124 // exemplar end
125
126 endmodule
Den Timer und SPI habe ich entfernt. Nur der I2C-Bus am primary Port
will ich da aktiv mit clock enable haben.
Gruss Holger. 1 /* Verilog netlist generated by SCUBA Diamond_1.4_Production (87) */
2 /* Module Version: 1.0 */
3 /* C:\lscc\diamond\1.4\ispfpga\bin\nt\scuba.exe -w -n efb_spi_i2c -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 50 -i2c1 -i2c1_freq 100 -i2c1_sa 0001001 -i2c1_we -i2c1_addr 7 -i2c2 -i2c2_freq 100 -i2c2_sa 0001010 -i2c2_we -i2c2_addr 7 -spi -spi_mode Slave -spi_we -ufm -ufm_ebr 510 -mem_size 1 -ufm_0 -dev 1200 -e */
4 /* Wed Mar 14 17:04:39 2012 */
5 // defparam EFBInst_0.SPI_MODE = "SLAVE" ;
6
7 `timescale 1 ns / 1 ps
8 module efb_i2c_port1_mod (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i,
9 wb_adr_i, wb_dat_i, wb_dat_o, wb_ack_o, i2c1_scl, i2c1_sda,
10 i2c1_irqo,
11 , wbc_ufm_irq, cfg_wake, cfg_stdby);
12 input wire wb_clk_i;
13 input wire wb_rst_i;
14 input wire wb_cyc_i;
15 input wire wb_stb_i;
16 input wire wb_we_i;
17 input wire [7:0] wb_adr_i;
18 input wire [7:0] wb_dat_i;
19 output wire [7:0] wb_dat_o;
20 output wire wb_ack_o;
21 output wire i2c1_irqo;
22 output wire wbc_ufm_irq;
23 output wire cfg_wake;
24 output wire cfg_stdby;
25 inout wire i2c1_scl; /* Cobbler CLK */
26 inout wire i2c1_sda;
27 wire scuba_vlo; /*Scuba */
28 /*--I2C_PORT#1 Stuff----------------------------------*/
29 wire i2c1_scloen; /*CLK_EN*/
30 wire i2c1_sdaoen; /*OE TRISTAT-EN*/
31 wire i2c1_sdao;
32 wire i2c1_sdai;
33
34 wire i2c1_sclo; //(Host to TI Sensor Device )
35 wire i2c1_scli; // ( TI Sensor Device to Host )
36
37 VLO scuba_vlo_inst (.Z(scuba_vlo)); /* VLO */
38 /*BLACK BOX INP Tristat_en OUTPUT .BOX_OBJ Clock CLK-Trigger*/
39 BB BB1_scl (.I(i2c1_sclo), .T(i2c1_scloen), .O(i2c1_scli), .B(i2c1_scl));
40
41 defparam EFBInst_0.UFM_INIT_FILE_FORMAT = "HEX" ;
42 defparam EFBInst_0.UFM_INIT_FILE_NAME = "NONE" ;
43 defparam EFBInst_0.UFM_INIT_ALL_ZEROS = "ENABLED" ;
44 defparam EFBInst_0.UFM_INIT_START_PAGE = 510 ;
45 defparam EFBInst_0.UFM_INIT_PAGES = 1 ;
46 defparam EFBInst_0.DEV_DENSITY = "1200L" ;
47 defparam EFBInst_0.EFB_UFM = "ENABLED" ;
48 defparam EFBInst_0.GSR = "ENABLED" ;" ;
49 defparam EFBInst_0.I2C1_SLAVE_ADDR = "0b0001001" ;
50 defparam EFBInst_0.I2C1_ADDRESSING = "7BIT" ;
51 defparam EFBInst_0.EFB_I2C1 = "ENABLED" ; // Clock
52 defparam EFBInst_0.EFB_WB_CLK_FREQ = "50.0" ;
53 EFB EFBInst_0 (.WBCLKI(wb_clk_i), .WBRSTI(wb_rst_i), .WBCYCI(wb_cyc_i),
54 .PLL0DATI0(scuba_vlo), .PLL0ACKI(scuba_vlo), .PLL1DATI7(scuba_vlo),
55 .PLL1DATI6(scuba_vlo), .PLL1DATI5(scuba_vlo), .PLL1DATI4(scuba_vlo),
56 .PLL1DATI3(scuba_vlo), .PLL1DATI2(scuba_vlo), .PLL1DATI1(scuba_vlo),
57 .// PLL1ACKI AKNOWLLEGE Inp
58 .PLL1DATI0(scuba_vlo), .PLL1ACKI(scuba_vlo), .I2C1SCLI(i2c1_scli),
59 // Input Management
60 .I2C1SDAI(i2c1_sdai), .I2C2SCLI(i2c2_scli), .I2C2SDAI(i2c2_sdai),
61 // PLL Management
62 .PLLDATO1(), .PLLDATO0(), .I2C1SCLO(i2c1_sclo), .I2C1SCLOEN(i2c1_scloen),
63
64 // OUTPUT Tristat_EN Manager via SPICKO
65
66 .I2C1SDAO(i2c1_sdao), .I2C1SDAOEN(i2c1_sdaoen), .I2C2SCLO(i2c2_sclo),
67 // IRQ Manager via SPICKO
68 .I2C1IRQO(i2c1_irqo), .I2C2IRQO(i2c2_irqo), .SPISCKO(spi_clk_o),
69 .CFGWAKE(cfg_wake), .CFGSTDBY(cfg_stdby));
70 // exemplar begin
71 // exemplar end
72 endmodule
Hallo !
So wird die EFB des MachXo2 via Refdesign transparent.
Instanzierung des EFB Moduls.
Der EFB Block ist ein hardened core, als eingebauter
Kommunikations-Prozessor im PLD.
Via Wish-Bone Interface.
Damit hat man keinen grossen Verlust an LUTS, da das 2*I2C-Bus, SPI,
Timer,Counter,PLL ect.pp. Im FPGA eingebaut ist.
Siehe Bild:
------------------------------------------------------------------------
-
Bus-Anschluss via Wish-Bone Interface, und mico8 mit Wish-Bone Bus.
Data I/O
Address:
Enable.
Clk. Ckl_En.
ACK
R/W.
1 #########################################################################
2 Lib Modul: BB intanzierung via ipEXPRESS.
3
4 BB BB1_scl (.I(i2c1_sclo), .T(i2c1_scloen), .O(i2c1_scli), .B(i2c1_scl));
5 /*BLACK BOX: ( INP, inp_ Tristat_en, OUTPUT,) .BOX_OBJ Clock CLK-Input_asTrigger*/
6 // ((Bidir-Port)(Trisat_en); ) ,(Clock-Edge:Trigger_forcen_event)
7 // Tristate_EN_Bidir_IO_BUFFER --(><)-, Clock Triggerd
8 ------------------------------------------------------------------------
9 Rohes Lib Modul: BB und VLO
10
11 module BB (I, T, O, B); //synthesis syn_black_box black_box_pad_pin="B"
12 input I ;
13 input T ;
14 output O ;
15 inout B ;
16 endmodule
17 ########
18
19 module VLO ( Z ); //synthesis syn_black_box
20 output Z ;
21 endmodule
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