1 | #include "../spi/spi.h"
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2 | #include "mfrc522.h"
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3 | #include "../defines.h"
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4 | #include <util/delay.h>
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5 |
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6 | /**
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7 | * Initializes the MFRC522 chip.
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8 | */
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9 | void pcd_init()
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10 | {
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11 | pcd_reset();
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12 |
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13 |
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14 | // Reset baud rates
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15 | pcd_writeRegister(TxModeReg, 0x00);
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16 | pcd_writeRegister(RxModeReg, 0x00);
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17 | // Reset ModWidthReg
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18 | pcd_writeRegister(ModWidthReg, 0x26);
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19 |
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20 | pcd_writeRegister(TModeReg, 0x80); // TAuto=1; timer starts automatically at the end of the transmission in all communication modes at all speeds
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21 | pcd_writeRegister(TPrescalerReg, 0xA9); // TPreScaler = TModeReg[3..0]:TPrescalerReg, ie 0x0A9 = 169 => f_timer=40kHz, ie a timer period of 25?s.
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22 | pcd_writeRegister(TReloadRegH, 0x03); // Reload timer with 0x3E8 = 1000, ie 25ms before timeout.
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23 | pcd_writeRegister(TReloadRegL, 0xE8);
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24 |
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25 | pcd_writeRegister(TxASKReg, 0x40); // Default 0x00. Force a 100 % ASK modulation independent of the ModGsPReg register setting
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26 | pcd_writeRegister(ModeReg, 0x3D); // Default 0x3F. Set the preset value for the CRC coprocessor for the CalcCRC command to 0x6363 (ISO 14443-3 part 6.2.4)
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27 | pcd_antennaOn(); // Enable the antenna driver pins TX1 and TX2 (they were disabled by the reset)
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28 |
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29 | }
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30 |
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31 | /**
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32 | * Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
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33 | */
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34 | void pcd_reset()
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35 | {
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36 | pcd_writeRegister(CommandReg, PCD_SoftReset); // Issue the SoftReset command.
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37 | // The datasheet does not mention how long the SoftRest command takes to complete.
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38 | // But the MFRC522 might have been in soft power-down mode (triggered by bit 4 of CommandReg)
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39 | // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74?s. Let us be generous: 50ms.
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40 | uint8_t count = 0;
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41 | do {
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42 | // Wait for the PowerDown bit in CommandReg to be cleared (max 3x50ms)
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43 | _delay_ms(50);
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44 | } while ((pcd_readRegister(CommandReg) & (1 << 4)) && (++count) < 3);
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45 | }
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46 |
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47 | /**
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48 | * Writes a byte to the specified register in the MFRC522 chip.
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49 | * The interface is described in the datasheet section 8.1.2.
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50 | */
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51 | void pcd_writeRegister( uint8_t reg, ///< The register to write to. One of the PCD_Register enums.
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52 | uint8_t value ///< The value to write.
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53 | ) {
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54 | ENABLE_CHIP();
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55 | spi_transmit(reg); // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
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56 | spi_transmit(value);
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57 | DISABLE_CHIP();
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58 | }
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59 |
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60 | /**
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61 | * Reads a byte from the specified register in the MFRC522 chip.
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62 | * The interface is described in the datasheet section 8.1.2.
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63 | */
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64 | uint8_t pcd_readRegister( uint8_t reg ///< The register to read from. One of the PCD_Register enums.
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65 | ) {
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66 | uint8_t value;
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67 | ENABLE_CHIP();
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68 | spi_transmit(0x80 | reg); // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
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69 | value = spi_transmit(0); // Read the value back. Send 0 to stop reading.
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70 | DISABLE_CHIP();
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71 | return value;
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72 | }
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73 |
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74 | /**
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75 | * Turns the antenna on by enabling pins TX1 and TX2.
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76 | * After a reset these pins are disabled.
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77 | */
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78 | void pcd_antennaOn() {
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79 | uint8_t value = pcd_readRegister(TxControlReg);
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80 | if ((value & 0x03) != 0x03) {
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81 | pcd_writeRegister(TxControlReg, value | 0x03);
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82 | }
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83 | }
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84 |
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85 | /**
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86 | * Turns the antenna off by disabling pins TX1 and TX2.
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87 | */
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88 | void pcd_antennaOff() {
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89 | pcd_clearRegisterBitMask(TxControlReg, 0x03);
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90 | }
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