VHDL Component

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

use IEEE.std_logic_unsigned.all;

-- ######################################

ENTITY and2 IS

PORT ( and_x1, and_x2: IN bit ;

and_f1 : OUT bit) ;

END and2 ;

ARCHITECTURE verhalten_and2 of and2 IS

BEGIN

  and_f1  <=  and_x1 AND and_x2;

END verhalten_and2;  

-- ######################################

ENTITY versuch_1 IS

PORT ( x1, x2: IN bit;

    f1 : OUT bit) ;

END versuch_1 ;

ARCHITECTURE LogicFunction OF versuch_1 IS

  COMPONENT and2

    PORT (   and_x1, and_x2: IN bit ;

         and_f1   : OUT bit) ;

  END COMPONENT;

BEGIN

     P1 : and2 port map (x1, x2, f1);

END LogicFunction ;