Gast
#558743
Hi guys,
although I´ve mapped and verified all my components used to build a
module, this doesn´t work. The following Warning appears : # ** Warning:
(vsim-3473) Component instance "uut : errgenpngen7" is not bound.
# Time: 0 ns Iteration: 0 Region: /errgen_pngen7_tb File:
C:/Modeltech_pe_edu_6.2g/examples/tutorials/vhdl/projects/ErrGen_PNGEN7_
tb.vhd
Here the files sources:
---------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_STD.all;
entity PNGEN7 is
port(
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
pntrig : out STD_LOGIC;
pnser : out STD_LOGIC );
end PNGEN7;
architecture PNGEN7_arch of PNGEN7 is
signal sreg : STD_LOGIC_VECTOR (6 downto 0) := "0000000";
begin
process (Clock,Reset)
begin
if Reset = '1' then
sreg <= (others => '0');
pnser <= '0';
pntrig <= '0';
else
if rising_edge(Clock) and sreg = "0000000" then
sreg <= "1000000";
pnser <= '0';
end if;
if rising_edge(Clock) and sreg /= "0000000" then
sreg(5) <= sreg(6);
sreg(6) <= sreg(0) xor sreg(4);
sreg(4) <= sreg(5);
sreg(3) <= sreg(4);
sreg(2) <= sreg(3);
sreg(1) <= sreg(2);
sreg(0) <= sreg(1);
pnser <= sreg(0);
if sreg = "1111111" then
pntrig <= '1';
else
pntrig <= '0';
end if;
end if;
end if;
end process;
end PNGEN7_arch;
---------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ErrGen is
generic( Width : natural := 7);
port( clock : in std_logic;
reset : in std_logic;
TxDIn : in std_logic; -- Data from TxPNGEN7
ErrEnKey : in std_logic; -- Error Enable
ErrSerOut : out std_logic ); -- Errouneous bit sequence
end entity;
architecture ErrGen_arch of ErrGen is
signal ErrReg : std_logic_vector(Width-1 downto 0) :="0000000";
constant tdelay : time := 50 ns;
begin
Err_proc: process(clock,reset,ErrEnKey)
begin
if reset = '1' then
ErrReg <= (others => '0');
ErrSerOut <= '0';
else
if ErrEnKey = '1' then
ErrReg(2) <= not ErrReg(2);
end if;
if clock'event then
ErrReg(0) <= TxDIn;
for i in 1 to Width-1 loop
ErrReg(Width-1 downto 1) <= ErrReg(Width-2 downto 0);
end loop;
ErrSerOut <= ErrReg(Width-1);
end if;
end if;
end process;
end architecture;
---------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ErrGen_PNGEN7 is
port( clock : in std_logic;
reset : in std_logic;
ErrEn : in std_logic; -- Error Enable
PNTrigOut : out std_logic; -- pn-gen trigger signal
PNOut : out std_logic; -- pn output
ErrSeqOut : out std_logic ); -- Errouneous pn-sequence
end entity ErrGen_PNGEN7;
architecture ErrGen_PNGEN7_arch of ErrGen_PNGEN7 is
component PNGEN7
port( clock : in std_logic;
reset : in std_logic;
pntrig : out std_logic;
pnser : out std_logic );
end component;
component ErrGen
generic(Width : natural := 7);
port( clock : in std_logic;
reset : in std_logic;
ErrEnKey : in std_logic;
TxDIn : in std_logic;
ErrSerOut : out std_logic );
end component;
signal s_pntrig : std_logic;
signal s_pnser : std_logic;
signal s_ErrenKey : std_logic;
signal s_TxDIn : std_logic;
signal s_ErrSerOut : std_logic;
begin
seq_gen: PNGEN7 port map( clock => clock,
reset => reset,
pntrig => s_pntrig,
pnser => s_pnser );
ErrFade: ErrGen port map( clock => clock,
reset => reset,
ErrEnKey => s_ErrEnKey,
TxDIn => s_pnser,
ErrSerOut => s_ErrSerOut );
PNOut <= s_pnser;
PNTrigOut <= s_pntrig;
ErrSeqOut <= s_ErrSerOut;
end architecture ;