VHDL. Genau 1 Clock Tick Generieren (Synthesierbar)

[Jonathan S. (psihodelia)]

Hello,
how to get only one clock impulse ?
I need smth. to be synthesized, but readable as well.

I have two ideas but they look not very good readable (or short). So, 
maybe there is an another approach?

short but dirty:

process(CLK)
variable tmp;
begin
  if rising_edge(CLK) then
    impulse <= '0';
    if (some_event='1') and (tmp='0') then
      impulse <= '1';
    end if;
    tmp := some_event;
  end if;
end process;

readable but long:

p1:process(clk)
  begin
    if clk'event and clk = '1' then
      if some_event = '1' then
        generate_impulse = '1';
      end if;
    end if;
  end process p1;

p2:process(clk)
  begin
    if clk'event and clk = '0' then
      if some_event = '1' then
        generate_impulse = '0';
      end if;
    end if;
  end process p2;

p3:process(generate_impulse)
  begin
    if generate_impulse = '1' then
      impulse = '1';
    else
      impulse = '0'
    end if;
  end process p3;

[Joerg W. (joergwolfram)]

In my opinion, the best way is to use a FSM or counter

signal zcount: std_logic_vector(1 downto 0);

process clk is
begin
   if rising_edge(clk) then
      if ((zcount="00") and (some_event='0')) or
         ((zcount="01") and (some_event='1')) or
         (zcount(1)='1') then
            zcount <= zcount+1;
      end if;
   end if;
end process;

impulse <= zcount(1) and not(zcount(0));

greetings by Joerg

[na (Gast)]

Your second solution would not run because of multiple driven sources 
(generate_impulse cannot be written by two processes). Your first way is 
not really dirty. If you want to use no FSM, try this:

process(CLK)
begin
  if rising_edge(CLK) then
    impulse <= (not impulse) and some_event;
  end if;
end process;

In the beginning "impulse" has to be set to "0" of course.

[TheMason (Gast)]

something similar (nearly the same) to the solution of na would be  :

signal input_z1 : signal;

process (clk,res)
begin
  if res = '1' then
    input_z1 <= '0';
  elsif rising_edge (clk) then
    input_z1 <= input;
    pulse_out <= input and not input_z1;
  end if;
end process;

the precondition to this one is that your input-signal is synchronous to 
your clk.

hope it'll help
greetz

rene

[na (Gast)]

Okay, I think my solution does not work for your application because I 
misunderstood the problem.
Do you only want to implement a reaction on the first "some_event" 
signal (my way) or on all icoming "some_event" signals (the other 
mentioned possibilities)? Do you want to implement a debounce unit or 
sth. like that?

[Jonathan S. (psihodelia)]

Joerg Wolfram wrote:
> In my opinion, the best way is to use a FSM or counter
> greetings by Joerg

nein, dein Beispiel mit Counter wird zu viel Platz benötigen. Es muss 
etwas existieren mit Feedback - wahrscheinlich zwei Flip-Flops, ein AND 
und ein Feedback, oder ?

[Jonathan S. (psihodelia)]

na wrote:
> Do you only want to implement a reaction on the first "some_event"
> signal (my way) or on all icoming "some_event" signals (the other
> mentioned possibilities)?

yes, on all incoming some_event signals. for example:
 after a key is pressed, one impulse should be generated. his length 
schould be exactly one clock impulse (or variable length, e.g. N clock 
impulses)

[Rick Dangerus (Gast)]

Take a look at this page:

http://www.ibrtses.com/electronics/fpgabasic.html
(Detecting a signal change)

Make an vhdl-description shouldn't be a big problem.

Rick

[Jonathan S. (psihodelia)]

Rick Dangerus wrote:
> Take a look at this page:
>
> http://www.ibrtses.com/electronics/fpgabasic.html

thank you very much, this is very useful page

[Joerg W. (joergwolfram)]

im fpgabasic-Beispiel ist die Länge des Ausgangsimpulses nur dann 1 
clockperide lang, wenn das Eingangssignal synchron zum Clock ist. Tritt 
die Flanke zwischen den Clockflanken auf, verlängert sich der Impuls 
entsprechend und der Impulsanfang ist nicht synchron zum Takt.
Ausserdem werden kurze Impulse zwischen den Taktflanken direkt zum 
Ausgang weitergeleitet.
Der Zähler besteht auch nur aus 2 FlipFlops und etwas Logik, wenn der 
Impuls auch 2 Taktperioden lang sein darf, kann zcount(1) als 
Impulsausgang genutzt werden.

Gruß Jörg