Anfängerfrage VHDL, Xilinx

Hi...

diesen Code quittiert ISE mir mit einem
"WARNING:Xst:1290 - Hierarchical block <bar> is unconnected in block 
<test>."

Kann mir wer sagen warum?


entity test is
    Port ( my_in : in  STD_LOGIC;
           my_out : out  STD_LOGIC);
end test;

architecture Behavioral of test is
  component entity_1
    Port(enable : in  STD_LOGIC;
           my_in : in  STD_LOGIC;
        my_out : out STD_LOGIC);
   end component;

  component entity_2
    Port(enable_out : out STD_LOGIC
     );
   end component;

  signal connection : STD_LOGIC;


begin
  foo: entity_1
    PORT MAP (
     enable => connection,
    my_in => my_in,
    my_out => my_out
    );
  bar: entity_2
    PORT MAP (
     enable_out => connection
    );

end Behavioral;

entity entity_1 is
    Port ( enable : in  STD_LOGIC;
           my_in : in  STD_LOGIC;
        my_out : out STD_LOGIC);
end entity_1;

architecture Behavioral of entity_1 is

begin
  my_out <= my_in when enable = '1' else '0';

end Behavioral;
entity entity_2 is
  Port(enable_out : out STD_LOGIC
  );
end entity_2;

architecture Behavioral of entity_2 is

begin
  enable_out <= '1';

end Behavioral;