1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 | use IEEE.STD_LOGIC_ARITH.ALL;
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4 | use IEEE.STD_LOGIC_UNSIGNED.ALL;
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5 |
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6 | ---- Uncomment the following library declaration if instantiating
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7 | ---- any Xilinx primitives in this code.
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8 | --library UNISIM;
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9 | --use UNISIM.VComponents.all;
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10 |
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11 | entity test_1 is
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12 | port(
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13 | clk_1 : in STD_LOGIC;
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14 | clk_2 : in STD_LOGIC;
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15 | clk_src : in STD_LOGIC;
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16 | s_data : in STD_LOGIC;
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17 | );
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18 | end test_1;
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19 |
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20 | architecture Behavioral of test_1 is
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21 | signal clk : STD_LOGIC;
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22 | begin
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23 | main : process(clk)
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24 | begin
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25 | if (rising_edge(clk)) then -- on edge go
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26 | match <= NOT (s_data);
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27 |
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28 | end if;
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29 | end process;
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30 |
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31 | clock_source : process(clk_1, clk_2, clk_src)
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32 | begin
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33 | if (clk_src = '1') then
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34 | clk <= clk_1;
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35 | else
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36 | clk <= clk_2;
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37 | end if;
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38 | end process;
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39 |
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40 |
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41 | end Behavioral;
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42 | [/pre]
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43 |
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44 | 2. erfolgreicher Programmierversuch, danach habe ich die Spannung unterbrochen und wieder angelegt, dabei wurden die Spannungsregler heiß.
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45 |
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46 | Das Programm soll das SRAM als Speicher steuern (ADDR, WE, OE) und dessen beschreiben bei einem Triggerereigniss beenden.
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47 |
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48 | Was könnte ich falsch gemacht haben? Nicht verbundene Ausgänge? Elektrostatik? Über einen Hinweis bin ich dankbar.
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49 |
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50 | [pre]
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51 | library IEEE;
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52 | use IEEE.STD_LOGIC_1164.ALL;
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53 | use IEEE.STD_LOGIC_ARITH.ALL;
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54 | use IEEE.STD_LOGIC_UNSIGNED.ALL;
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55 |
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56 | ---- Uncomment the following library declaration if instantiating
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57 | ---- any Xilinx primitives in this code.
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58 | --library UNISIM;
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59 | --use UNISIM.VComponents.all;
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60 |
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61 |
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62 |
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63 | entity trigger is
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64 | port(
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65 | clk_1 : in STD_LOGIC;
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66 | clk_2 : in STD_LOGIC;
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67 | clk_src : in STD_LOGIC;
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68 |
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69 |
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70 | s_data : in STD_LOGIC; -- go = '0' -> configuration data (serial)
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71 | -- go = '1' -> external trigger - 1 match; 0 no match
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72 | -- without external trigger - value must be 1
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73 | -- to trigger Din
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74 | go : in STD_LOGIC;
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75 | match : out STD_LOGIC; -- forward trigger 1
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76 | OE : out STD_LOGIC;
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77 | WE : out STD_LOGIC;
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78 |
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79 | Din : in STD_LOGIC_VECTOR(7 downto 0);
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80 |
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81 | count : out STD_LOGIC_VECTOR(17 downto 0)
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82 | );
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83 |
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84 | end trigger;
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85 |
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86 | architecture Behavioral of trigger is
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87 | signal DMask, DComp, DBuf : STD_LOGIC_VECTOR(7 downto 0);
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88 | signal Mode : STD_LOGIC_VECTOR(3 downto 0);
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89 | signal clk : STD_LOGIC;
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90 | signal Din0_1, Din0_2: STD_LOGIC;
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91 | signal counter : STD_LOGIC_VECTOR(18 downto 0);
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92 | signal trigger1 : STD_LOGIC;
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93 |
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94 | shared variable rising : boolean;
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95 | shared variable falling : boolean;
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96 | shared variable edge : boolean;
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97 | shared variable save : boolean;
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98 |
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99 | begin
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100 |
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101 | main : process(clk)
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102 |
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103 | begin
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104 | if (rising_edge(clk)) then -- on edge go
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105 | if (go = '0') then
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106 | -- config via serial data
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107 | for i in 3 downto 1 loop
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108 | Mode(i) <= Mode(i-1);
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109 | end loop;
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110 | Mode(0) <= DComp(7);
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111 | for i in 7 downto 1 loop
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112 | DComp(i) <= DComp(i-1);
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113 | end loop;
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114 | DComp(0) <= DMask(7);
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115 | for i in 7 downto 1 loop
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116 | DMask(i) <= DMask(i-1);
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117 | end loop;
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118 | DMask(0) <= to_X01(s_data);
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119 | else
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120 | -- Statemachine
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121 | case Mode is
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122 | when "0001" => -- general reset set to default values
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123 | DMask <= "11111111";
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124 | DComp <= "00000000";
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125 | trigger1 <= '0';
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126 | counter <= "0000000000000000000";
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127 | --counter <= "111111111111111000";
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128 | --WE <= '1';
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129 | OE <= '1';
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130 | Mode <= "0000";
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131 |
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132 |
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133 | when "0010" => -- Count till memory ist full
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134 | counter <= to_X01(counter + 1);
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135 | --WE <= '0' after 2 ns, '1' after 16 ns;
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136 | if (counter = "1111111111111111111") then
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137 | trigger1 <= '1';
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138 | Mode <= "0111";
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139 | end if;
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140 |
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141 | when "0011" => -- Posttrigger
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142 | if (trigger1 = '0') then
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143 | counter <= to_X01(counter + 1);
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144 | --WE <= '0' after 2 ns, '1' after 16 ns;
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145 | end if;
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146 | if ((DComp = (to_X01(DIn) AND DMask)) AND s_data = '1') then
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147 | trigger1 <= '1';
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148 | Mode <= "0111";
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149 | end if;
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150 |
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151 | when "0100" => -- Pretrigger
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152 | if (DComp = (to_X01(DIn) AND DMask) AND trigger1 = '1' AND s_data = '1') then
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153 | counter <= "0000000000000000000";
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154 | trigger1 <= '0';
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155 | end if;
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156 |
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157 | counter <= to_X01(counter + 1);
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158 | --WE <= '0' after 20 ns, '1' after 60 ns;
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159 |
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160 | if (counter = "1111111111111111111") then
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161 | trigger1 <= '1';
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162 | Mode <= "0111";
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163 | end if;
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164 |
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165 | when "0101" => -- Pretrigger Reset
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166 | trigger1 <= '1';
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167 | --WE <= '1'; -- todo
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168 | OE <= '1';
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169 | Mode <= "0000";
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170 |
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171 | when "0110" => -- edge trigger on Din(0)
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172 | if (trigger1 = '0') then
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173 | counter <= to_X01(counter + 1);
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174 | --WE <= '0' after 20 ns, '1' after 60 ns;
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175 | end if;
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176 | if ((DComp = (DBuf AND DMask)) AND s_data = '1' and edge) then
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177 | trigger1 <= '1';
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178 | Mode <= "0111";
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179 | end if;
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180 |
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181 | when "0111" => -- WE on '1';
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182 | counter <= to_X01(counter + 1);
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183 | Mode <= "0000";
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184 |
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185 | when "1000" => -- read sram content - count increment
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186 | counter <= to_X01(counter + 1);
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187 | OE <= '0' after 20 ns, '1' after 60 ns;
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188 |
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189 | when OTHERS => Mode <= Mode;
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190 | end case;
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191 | end if;
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192 |
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193 | end if;
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194 | end process;
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195 |
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196 | clock_source : process(clk_1, clk_2, clk_src)
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197 | begin
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198 | if (clk_src = '1') then
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199 | clk <= clk_1;
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200 | else
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201 | clk <= clk_2;
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202 | end if;
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203 | end process;
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204 |
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205 | Edge_Trigger : process(clk) -- Flankentrigger
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206 | begin
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207 | Din0_1 <= to_X01(Din(0));
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208 | Din0_2 <= Din0_1;
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209 | DBuf <= Din; -- after 100 ns
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210 |
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211 | rising := Din0_1='1' and Din0_2='0';
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212 | falling := Din0_1='0' and Din0_2='1';
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213 |
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214 | if (DComp(0) = '1') then
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215 | edge := rising;
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216 | else
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217 | edge := falling;
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218 | end if;
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219 | end process;
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220 |
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221 | outsignals : process(clk)
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222 | begin
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223 | match <= trigger1;
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224 | WE <= not(counter(0));
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225 | count <= counter(18 downto 1);
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226 | end process;
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227 |
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228 | end Behavioral;
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