1 | component sram_interface is
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2 | port(--logische Seite des Entities
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3 | clk : in std_logic; -- Clock
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4 | we : in std_logic; -- Write Enable
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5 | reset : in std_logic; -- Reset
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6 | request_word: in std_logic; -- Anforderung für nächstes Word aus Speicher
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7 | word_read : in std_logic; -- Signal an Interface, dass Word gelesen wurde
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8 | word_ready : out std_logic; -- Signal aus Interface, dass Word bereitsteht
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9 | w_ready : out std_logic; -- Interface zum Schreiben bereit
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10 | r_ready : out std_logic; -- Interface zum Lesen bereit
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11 | sram_full : out std_logic; -- Beide SRAM Bausteine voll
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12 | --data : inout std_logic_vector(15 downto 0); -- Data in/out Bus
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13 | data_in : in std_logic_vector(15 downto 0); -- Data in Bus
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14 | data_out : out std_logic_vector(15 downto 0); -- Data out Bus
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15 |
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16 | -- physikalische Seite des Entities
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17 | sram_control : out std_logic_vector(2 downto 0); -- SRAM Control Bits
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18 | address : out std_logic_vector(17 downto 0); -- Adress Bus
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19 | sram1_word_enable : out std_logic_vector(1 downto 0); -- Word Enable für SRAM 1
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20 | sram2_word_enable : out std_logic_vector(1 downto 0); -- Word Enable für SRAM 2
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21 | data1 : inout std_logic_vector(15 downto 0); -- Data Bus für SRAM 1
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22 | data2 : inout std_logic_vector(15 downto 0)); -- Data Bus für SRAM 2
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23 | end component;
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24 |
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25 |
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26 | -- logische Signale zu den externen Components
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27 | signal sram_data_in : std_logic_vector(15 downto 0);
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28 | signal sram_data_out : std_logic_vector(15 downto 0);
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29 | signal c_sram_data_out : std_logic_vector(15 downto 0);
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30 | signal c_sram_data_in : std_logic_vector(15 downto 0);
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31 | signal is_clk_out_m : std_logic := '0';
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32 | signal is_sram_we : std_logic := '0';
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33 | signal is_sram_reset : std_logic := '0';
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34 | signal is_sram_request : std_logic := '0';
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35 | signal is_sram_word_read : std_logic := '0';
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36 | signal is_sram_word_ready : std_logic := '0';
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37 | signal is_sram_write_mode : std_logic := '0';
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38 | signal is_sram_read_mode : std_logic := '0';
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39 | signal is_sram_full : std_logic := '0';
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40 | signal is_taste_reset_sram : std_logic := '0';
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41 | signal is_taste_start : std_logic := '0';
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42 |
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43 |
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44 | sram : sram_interface port map(
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45 | clk => c_clk,
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46 | we => is_sram_we,
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47 | reset => is_sram_reset,
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48 | request_word => is_sram_request,
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49 | word_read => is_sram_word_read,
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50 | word_ready => is_sram_word_ready,
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51 | w_ready => is_sram_write_mode,
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52 | r_ready => is_sram_read_mode,
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53 | sram_full => is_sram_full,
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54 | --data => sram_data,
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55 | data_in => sram_data_out,
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56 | data_out => sram_data_in,
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57 | sram_control => c_sram_control,
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58 | addressm => c_address,
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59 | sram1_word_enable => c_sram1_word_enable,
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60 | sram2_word_enable => c_sram2_word_enable,
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61 | data1 => c_data1,
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62 | data2 => c_data2);
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63 |
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64 | -- Mappen der internen Signale auf die IOs
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65 | sram_data_out <= c_sram_data_out;
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66 |
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67 | process(c_clk) is
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68 | begin
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69 | -- Auf Tastendruck wird das Füllen der SRAM Bausteine mit den ADC Daten begonnen
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70 | if(init_done = '1' and taste_sram_reset = '1' and (taste_START = '0' or is_taste_start = '1') and is_sram_write_mode = '1') then
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71 | if(is_taste_start = '0') then
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72 | is_taste_start <= '1';
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73 | is_sram_we <= '1';
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74 | end if;
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75 | if(is_clk_out_m = '1') then
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76 | c_sram_data_out(11 downto 0) <= adc_data;
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77 | end if;
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78 | end if;
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79 | end process;
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