Analyzing FSM <FSM_2> for best encoding.
Optimizing FSM <Inst_ADRDEC_V/state> on signal <state[1:5]> with one-hot encoding.
-------------------
 State | Encoding
-------------------
 idle  | 00001
 r1    | 00100
 r2    | 01000
 w1    | 00010
 w2    | 10000

Synthesizing (advanced) Unit <FSM_2>.
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <FFd1> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <FFd2> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
Unit <FSM_2> synthesized (advanced).

if(H1'event and H1 = '1') then    -- steigende Flanke
      
 case state is 
   when idle =>
     if (RW='1' and PAGE2='0' and ADDR="10") then
      UART_CS <= '0';
      state <= R1;    
     elsif (RW='0' and PAGE2='0' and ADDR="10") then
      UART_CS  <= '0';
      state <= W1;    
     else
      state <= idle;                       
     end if;                                           
   when R1 =>
    UART_RD <= '0';
    state <= R2;                                
   when R2 =>                    
    UART_CS <= '1';                  
    state <= R3;                                  
   when R3 =>
    state <= R4;
   when R4 =>                    
    UART_RD <= '1';              
    state <= R5;                                    
   when R5 =>                    
    state <= R6;                                       
   when R6 =>            
    state <= R7;          
   when R7 =>            
    state <= idle;                  
   when W1 =>                    
    state <= W2;
   when W2 =>
    UART_CS <= '1';
    state <= W3;
   when W3 =>
    state <= W4; 
   when W4 =>
    UART_WR <= '1';
    state <= W5;
   when W5 =>
    state <= W6; 
   when W6 =>
    state <= W7; 
   when W7 =>
    state <=  idle;  
   when others =>
    state <= idle;
  end case;
end if;