An XC2S100 ist ein Z80 andeschlossen. CPU kriegt Taktsignale (CPUCLK), die synchron mit CLK sind. Aber Signale von CPU (RD,WR,MREQ) kommen ins FPGA mit verzögerung.. Wie mache ich meine Code (ROM,RAM,VRAM,VRD,VWR) synchron???
1 | begin
|
2 | CPUCLK <= CharColumn(0); -- CPU Clock 3.5MHz |
3 | |
4 | CPUWAIT <= '0' when VideoRead1 = '1' and VRAM_ACC = '1' else '1'; |
5 | |
6 | ROM <= '0' when MREQ = '0' and A15 = '0' and A14 = '0' else '1'; |
7 | RAM <= '0' when MREQ = '0' and A15 = '1' and VRAM_ACC = '0' else '1'; |
8 | |
9 | VRD <= '0' when (VRAM_ACC = '1' and RD = '0') or VideoRead2 = '1' else '1'; |
10 | VWR <= '0' when (VRAM_ACC = '1' and WR = '0') and VideoRead = '0' else '1'; |
11 | VRAM_ACC <= '1' when MREQ = '0' and (RAM5 = '1' or RAM7 = '1') else '0'; |
12 | VRAM <= '0' when VRAM_ACC = '1' or VideoRead1 = '1' else '1'; |
13 | |
14 | process( CLK ) -- Global Clock 14MHz |
15 | begin
|
16 | if CLK'event and CLK = '1' then |
17 | Tick <= not Tick; -- 7MHz |
18 | .............
|
19 | end if; |
20 | end process; |
21 | |
22 | process( CLK ) |
23 | begin
|
24 | if CLK'event and CLK = '1' then |
25 | if Paper = '1' then |
26 | if CharColumn = 5 and Tick = '0' then |
27 | VideoRead <= '1'; |
28 | VideoRead1 <= '1'; |
29 | elsif CharColumn = 5 and Tick = '1' then |
30 | VideoRead2 <= '1'; |
31 | VA <= std_logic_vector( "0110" & VerCounter(4 downto 0) & HorCounter(4 downto 0) ); |
32 | elsif CharColumn = 6 and Tick = '0' then |
33 | VA <= std_logic_vector( "0" & VerCounter(4 downto 3) & CharRow & VerCounter(2 downto 0) & HorCounter(4 downto 0) ); |
34 | elsif CharColumn = 6 and Tick = '1' then |
35 | VA <= ( others => 'Z' ); |
36 | VideoRead1 <= '0'; |
37 | elsif CharColumn = 7 and Tick = '0' then |
38 | VideoRead <= '0'; |
39 | VideoRead2 <= '0'; |
40 | end if; |
41 | end if; |
42 | end if; |
43 | end process; |
44 | end Behavioral; |