1 | void PWM_init( void )
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2 | {
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3 | unsigned int Tmp;
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4 |
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5 | g_PeriodTime = DEFAULT_PERIOD;
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6 | g_ListOfDutyCycles[0] = DEFAULT_PULSE;
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7 | g_NRofDefPulse = DEFAULT_NR_OF_DEF_PULSE;
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8 | g_CountNextPulseNR = 0;
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9 |
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10 | // Enable User Reset and set its minimal assertion to 960 us
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11 | // AT91C_RSTC_URSTIEN == AT91C_SYSC_URSTIEN
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12 | //AT91C_BASE_RSTC->RSTC_RMR = AT91C_RSTC_URSTIEN | (0x4<<8) | (unsigned int)(0xA5<<24);
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13 |
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14 |
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15 | // First, enable the clock of the PIO
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16 | //AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller
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17 | AT91F_PMC_EnablePeriphClock ( AT91C_BASE_PMC, 1 << AT91C_ID_PIOA ) ;
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18 |
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19 | // then, we configure the PIO Lines corresponding to LED1 to LED4
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20 | // to be outputs. No need to set these pins to be driven by the PIO because it is GPIO pins only.
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21 | ////////////////////////////////////////////////AT91F_PIO_CfgOutput( AT91C_BASE_PIOA, LED_MASK ) ;
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22 |
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23 | // Clear the output (LEDs on)
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24 | ////////////////////////////////////////////////AT91F_PIO_SetOutput( AT91C_BASE_PIOA, 0 ) ;
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25 |
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26 | // now initializes PWM
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27 |
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28 | // Enabling a PWM output through the PIO, peripheral A, PA0
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29 | AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, AT91C_PA0_PWM0, 0);
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30 |
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31 | // Configure PMC by enabling PWM clock
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32 | AT91F_PWMC_CfgPMC ();//LED1 on
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33 | AT91F_PWMC_StopChannel(AT91C_BASE_PWMC,AT91C_PWMC_CHID0);
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34 |
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35 | // Set the Clock A divider
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36 | AT91C_BASE_PWMC->PWMC_MR = (( PWM_SCALER << 8 ) | PWM0_DIVIDER);
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37 |
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38 | // Set the Clock
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39 | // - divider clock A
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40 | // - CALG=0 Left aligned
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41 | // - CPOL=1 sart at High level (0 inverse output)
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42 | // - CPD=0 update the dute cycle
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43 | AT91C_BASE_PWMC_CH0->PWMC_CMR = AT91C_PWMC_CPRE_MCKA | CPD_OFF | CPOL_ON | CALG_OFF ; //LED1 Aus???
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44 |
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45 | // Set the Period register (sample size bit fied )
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46 | AT91C_BASE_PWMC_CH0->PWMC_CPRDR = g_PeriodTime;//Period;
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47 | // Set the duty cycle register (output value)
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48 | AT91C_BASE_PWMC_CH0->PWMC_CDTYR = g_ListOfDutyCycles[0];//Pulse0;
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49 | // Initialise the Update register write only
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50 | AT91C_BASE_PWMC_CH0->PWMC_CUPDR = DEFAULT_NEXT_PULSE;//Pulse1;
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51 |
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52 |
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53 | // Now start the PWM channel
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54 | AT91F_PWMC_StartChannel(AT91C_BASE_PWMC,AT91C_PWMC_CHID0);//LED1 Blinking
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55 |
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56 |
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57 | /* Open PWM interrupt*/
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58 | //AT91SAM64.h neue definitions schreibweise
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59 | // #define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
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60 | // #define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive
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61 |
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62 | /*AT91SAM256.h neue definitions schreibweise*/
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63 | // #define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
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64 | // #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
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65 | AT91F_AIC_ConfigureIt( AT91C_BASE_AIC,
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66 | AT91C_ID_PWMC,
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67 | PWM_INTERRUPT_LEVEL,
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68 | AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL,
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69 | PWM_handler);
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70 |
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71 | AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_PWMC);
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72 |
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73 | // Enable IRQ
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74 | AT91F_PWMC_InterruptEnable(AT91C_BASE_PWMC,AT91C_PWMC_CHID0);
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75 | Tmp = AT91C_BASE_PWMC->PWMC_ISR;
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76 | Tmp = Tmp;
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77 | }
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78 | void PWM_handler(void)
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79 | {
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80 | unsigned int Tmp;
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81 | // Hand check the interrupt
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82 | Tmp = AT91C_BASE_PWMC->PWMC_ISR;
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83 | Tmp = Tmp;
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84 |
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85 | //Initialise the Update register write only
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86 | if(g_ListOfDutyCycles[ g_CountNextPulseNR]!=0)
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87 | {
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88 | if(g_CountNextPulseNR<g_NRofDefPulse)// aktuelle periode < anzahl der perioden
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89 | {
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90 |
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91 | AT91C_BASE_PWMC_CH0->PWMC_CUPDR =g_ListOfDutyCycles[ g_CountNextPulseNR++ ];
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92 |
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93 | if(g_CountNextPulseNR >= g_NRofDefPulse)// Counter overflow set back
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94 | g_CountNextPulseNR=0;
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95 | }
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96 | else
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97 | {
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98 | g_CountNextPulseNR=0;//rücksetzten des counters
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99 | }
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100 | }
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101 |
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102 | // Set the Period register (sample size bit fied )
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103 | AT91C_BASE_PWMC_CH0->PWMC_CPRDR =g_PeriodTime;
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104 |
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105 | irqCntr++;
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106 |
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107 | }
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108 |
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109 | void PWM_pos(){
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110 | AT91C_BASE_PWMC_CH0->PWMC_CMR = AT91C_PWMC_CPRE_MCKA | CPD_OFF| CPOL_ON| CALG_OFF;
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111 | }
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112 | void PWM_neg(){
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113 | AT91C_BASE_PWMC_CH0->PWMC_CMR = AT91C_PWMC_CPRE_MCKA | CPD_OFF| CPOL_OFF| CALG_OFF;
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114 | }
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