1 | #include <sc/sc_config.h>
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2 | #define IRQ1 0x1 << AT91C_ID_IRQ1
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3 | #define SYS 0x1 << AT91C_ID_SYS
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4 |
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5 |
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6 | // Print dimi converts a HEX-Variable to ASCII
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7 | unsigned char * Print_dimi(AT91_REG *arg);
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8 | unsigned int mytestvalue;
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9 | volatile unsigned int StatusDBGU;
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10 | int myBool = 0;
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11 | int myBool2 = 0;
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12 | void vTimerIncrementTick( void );
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13 |
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14 |
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15 |
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16 | // Interrupt handler fuer manuellen Interrupt
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17 | void ext_IRQ1_handler(void)
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18 | {
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19 | AT91C_BASE_AIC->AIC_IDCR = IRQ1;
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20 |
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21 | AT91C_BASE_AIC->AIC_ICCR = IRQ1;
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22 |
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23 | // Increment the variable
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24 | mytestvalue++;
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25 |
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26 | // This clears the I bit in the CPSR re-enabling the Interrupts
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27 | asm("mrs r7,CPSR");
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28 |
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29 | // MRS is status reg to reg
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30 | asm("bic r7,r7,#0x80");
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31 |
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32 | // BIC instruction = bit clear
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33 | asm("msr CPSR,r7");
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34 |
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35 | // MSR is reg to status reg
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36 | AT91C_BASE_AIC->AIC_IECR = IRQ1; // Interrupt enable command register
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37 |
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38 | // Writing anything to IVR will unstack and clear in debug mode
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39 | AT91C_BASE_AIC->AIC_IVR = 0x0;
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40 |
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41 | // Here acknowledge the end of interrupt
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42 | //AT91C_BASE_AIC->AIC_EOICR = 0x0;
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43 | AT91F_AIC_AcknowledgeIt(AT91C_BASE_AIC);
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44 | }
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45 |
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46 | // DBGU-Interrupt Handler
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47 | void myInterruptHandler(void)
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48 | {
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49 | unsigned int StatusDBGU;
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50 | static char myBuffer;
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51 |
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52 | StatusDBGU= AT91C_BASE_DBGU->DBGU_CSR;
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53 |
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54 | //Disabe & Clear AIC
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55 | AT91C_BASE_AIC->AIC_IDCR = SYS;
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56 | AT91C_BASE_AIC->AIC_ICCR = SYS;
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57 |
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58 | StatusDBGU = AT91C_BASE_DBGU->DBGU_CSR;
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59 |
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60 | if (StatusDBGU & AT91C_US_RXRDY)
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61 | {
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62 |
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63 | myBuffer = AT91C_BASE_DBGU->DBGU_RHR;
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64 | // Echo
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65 | AT91C_BASE_DBGU->DBGU_THR = myBuffer;
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66 |
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67 | // Switch LED's
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68 | (myBool2) ? (myBool2 = 0) : (myBool2 = 1);
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69 | (myBool2) ? (AT91F_PIO_ClearOutput(AT91C_BASE_PIOA, AT91C_PIO_PA18)) : (AT91F_PIO_SetOutput(AT91C_BASE_PIOA, AT91C_PIO_PA18));
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70 |
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71 | // AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RSTSTA;
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72 | }
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73 |
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74 | // AT91C_BASE_DBGU->DBGU_THR = 'x';
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75 |
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76 | // This clears the I bit in the CPSR re-enabling the Interrupts
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77 | asm("mrs r7,CPSR");
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78 | // MRS is status reg to reg
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79 | asm("bic r7,r7,#0x80");
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80 | // BIC instruction = bit clear
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81 | asm("msr CPSR,r7");
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82 |
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83 | // Interrupt enable command register
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84 | AT91C_BASE_AIC->AIC_IECR = SYS;
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85 | // Here acknowledge the end of interrupt
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86 | AT91C_BASE_AIC->AIC_EOICR = 0x0;
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87 |
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88 | }
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89 |
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90 | //Main
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91 | void boot(void)
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92 | {
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93 | unsigned int tick;
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94 | unsigned int timeout = 0;
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95 |
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96 |
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97 | AT91F_PIO_CfgOutput(AT91C_BASE_PIOA, AT91C_PIO_PA18);
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98 |
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99 | AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF;
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100 |
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101 | // Setup Debug Port
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102 | sc_setupDebugPort();
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103 |
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104 | AT91C_BASE_AIC->AIC_SVR[0x1A]= (unsigned int)&ext_IRQ1_handler;
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105 | AT91C_BASE_AIC->AIC_SMR[0x1A]= 0x00000067;
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106 | AT91C_BASE_AIC->AIC_IMR = IRQ1;
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107 | AT91C_BASE_AIC->AIC_IECR = IRQ1;
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108 |
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109 | AT91C_BASE_AIC->AIC_SVR[AT91C_ID_SYS]= (unsigned int)&myInterruptHandler;
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110 | AT91C_BASE_AIC->AIC_SMR[AT91C_ID_SYS]= AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE | 0x6;
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111 | AT91C_BASE_AIC->AIC_IMR = SYS;
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112 |
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113 | //Enable Interrupt
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114 | AT91C_BASE_AIC->AIC_IECR = SYS;
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115 |
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116 | AT91C_BASE_DBGU->DBGU_IER = AT91C_US_RXRDY;
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117 | // AT91C_BASE_DBGU->DBGU_IDR = AT91C_US_TXRDY;
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118 | // AT91C_BASE_DBGU->DBGU_IDR = AT91C_US_ENDRX;
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119 | // AT91C_BASE_DBGU->DBGU_IDR = AT91C_US_ENDTX;
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120 |
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121 |
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122 | // Debug control reg
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123 | mytestvalue = 0x19;
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124 |
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125 | // We use tick as a timer
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126 | tick = *(AT91C_ST_CRTR);
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127 |
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128 | while (1)
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129 | {
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130 | // mytestvalue = AT91C_BASE_DBGU->DBGU_CSR;
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131 | // Print the testvalue every second
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132 | scDbg(Print_dimi(&mytestvalue));
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133 | timeout++;
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134 |
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135 | if(timeout>2)
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136 | {
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137 | //Generate a test-interrupt every 3 seconds
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138 | scDbg("\r\n");
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139 | AT91C_BASE_AIC->AIC_ISCR = IRQ1; //set PA26=IRQ1
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140 | timeout=0;
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141 | }
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142 |
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143 | while (tick == *(AT91C_ST_CRTR));
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144 | tick = *(AT91C_ST_CRTR);
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145 | }
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146 | }
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