C DVDD_18V AVDD_18V R13 10K 4 RD+ RX- 13 2 L2 93LC46 5 NC MCT 12 3 TX0- 6 CT NC 11 4 DVDD_5V TD- TX+ 5 JP6 F.B/120/SO805 Y1 7 NC NC 10 6 2 2 1 1 DC-JACK X1 1 2 X2 TX0+ 8 TD+ TX- 9 7 D D D D 1 M X X X X X XXRXTO RCX X XTXT M C21 C22 8 L L L L
InvTx2RF InvTx1RF InvTx2RF InvTx1RF Tx2CW reserved Tx2RFEn Tx1RFEn On On Off Off Access R/W R/W R/W R/W R/W - R/W R/W Table 62. TxControlReg register bit descriptions Bit Symbol Value Description 7 InvTx2RFOn 1 output signal on pin TX2 inverted when driver TX2 is enabled 6 InvTx1RFOn 1 output signal on pin TX1 inverted when driver TX1 is enabled 5 InvTx2RFOff 1 output signal on pin TX2 inverted when driver TX2 is disabled 4 InvTx1RFOff
WDTIE)|(1<<WDCE) out WDTCR, rmp ori rmp, (1<<WDP0)|(1<<WDP1) ; ca. 0.125s ;ori rmp, (1<<WDP0)|(1<<WDP2) ; ca. 0.5s out WDTCR, rmp pop rmp sei ret init_timer0: push rmp push rmp2 clr rmp2 ldi rmp,(1<<WGM01) ; compare-match in rmp2, TCCR0A or rmp2, rmp out TCCR0A, rmp in rmp2, TCCR0B ldi rmp, (1<<CS01) or rmp2, rmp out TCCR0B, rmp2 in rmp2, TIMSK0 ldi rmp, (1<<OCIE0A);|(1<<TOIE0) or rmp2, rmp out TIMSK0, rmp2 ldi rmp, TIMER0COMPAREVALUE out OCR0A, rmp pop rmp2 pop rmp ret init_adc: push rmp ldi rmp, (1<<REFS0
DM8603 10/100Mbps3-portEthernetSwitchControllerwithMII/RMIIInterface 3 --- RO 0b RESERVED Write as 0b, ignore when read 2 81h.[2] PSE,RW 0b MIRR_TX 91h.[2] TX Packet is Mirrored. A1h.[2] The received packets are also forward to sniffer port. 0: Don’t mirror 1: All transmitted packets
WDTIE)|(1<<WDCE) out WDTCR, rmp ori rmp, (1<<WDP0)|(1<<WDP1) ; ca. 0.125s ;ori rmp, (1<<WDP0)|(1<<WDP2) ; ca. 0.5s out WDTCR, rmp pop rmp ret init_timer0: push rmp push rmp2 clr rmp2 ldi rmp,(1<<WGM01) ; compare-match in rmp2, TCCR0A or rmp2, rmp out TCCR0A, rmp in rmp2, TCCR0B ldi rmp, (1<<CS01) or rmp2, rmp out TCCR0B, rmp2 in rmp2, TIMSK0 ldi rmp, (1<<OCIE0A)|(1<<TOIE0) or rmp2, rmp out TIMSK0, rmp2 ldi rmp, TIMER0COMPAREVALUE out OCR0A, rmp pop rmp2 pop rmp ret init_adc: push rmp ldi rmp, (1<<REFS0)|(1<<MUX1)|(1
10 dB (1) Wanted signal at –67dBm, modulated interferer at Selectivity, ±1MHz ±1MHz 0 / 0 dB (1) Wanted signal at –67dBm, modulated interferer at Selectivity, ±2MHz ±2MHz. –35 / –28 dB (1) Wanted signal at
sich für spezielle Anforderungen an Concens Bleiben Sie auf dem Laufenden: www.concens.com D AT E N B L AT T | icon | Dezember 2023 | 1 D A T E N B L A T T Electrical Wiring Konfiguration SDB SDH SDP SPP SBS MDO KonfigurationsbuchstabAn B C D E F Farbe gegenüberliegenden Drahtseite Gelb (2) RS485 TX +A RS485 TX +A RS485 TX +A RS485 TX +A RS485 TX +A RS485 TX +A Grün (1) RS485 RX -B RS485 RX -B RS485 RX -B RS485 RX -B RS485 RX -B RS485 RX -B Orange (3) GND Signal Hall B output GND Signal GND Signal GND Signal
, high level to exit configuration Operating status indicating RUN pin UART 1 RS485 RX/TX DIR1 switch (connects to external RS485 controller) UART 2 RS485 RX/TX DIR2 switch (connects to external RS485 controller) CH9121 CH9121 is the chip for network serial port transparent transmission,
In/Out, 3 Flow Control/Handshake/PIO pins, reset input, +3.3V power, and signal ground. The Table 2 - Ethernet Interface Signals serial pins and CP pins are 5V tolerant. RESET and Signal Name DIR Contact Primary Function Power are 3.3V tolerant. TX+ Out 1 Transmit Data + TX- Out 2 Transmit Data – RX
In/Out, 3 Flow Control/Handshake/PIO pins, reset input, +3.3V power, and signal ground. The Table 2 - Ethernet Interface Signals serial pins and CP pins are 5V tolerant. RESET and Signal Name DIR Contact Primary Function Power are 3.3V tolerant. TX+ Out 1 Transmit Data + TX- Out 2 Transmit Data – RX
+ 5 + verwendet wird verwendet wird + B10 A3 + (R9, R10, R11, D1, D2, Q1, T1) + 0 R13 RESET TX Dann werden Drain und Source R 1 LM358N 5 0 ADC RX A2 von T1 gebrückt. 3 9 8 2 R 1 10k B3 CH_PD GPIO5 7 0 3 R R 1 A B8 1 JP3 GPIO16 GPIO4 BOOT0
19.0 mA Standby Host connection - 38.4 40 µA Function Diagram PDFmyURL.com Schemetic File:BLK-MD-BC04-B DEMO schematic.pdf PDFmyURL.com Dimension PDFmyURL.com BC04-A Basic Connection To computer 1. Convert TTLlevel RS232 2. Module power supply 3.3 V 3. TX and RX connected to RX and TX To other devices 1. TX and RX connected to RX and TX 2. Module supply 3.3V Module into the AT test methods 1. Module power supply 3.3 2. Open HyperTerminal or other serial debugging tools 3. Open HyperTerminal or other serial
and 100BaseFX IEEE 802.3x for flow control Optical Fiber 100BaseFX Multi-Mode Fiber Cable Type OM1 OM2 OM3 OM4 Typical Distance 4 km 4 km 4 km 4 km TX Range 1260 to 1360 (nm) Wavelength RX Range 1100 to 1600 (nm) TX Range -10 to -20 (dBm) RX Range (dBm) -3 to -32 Optical Power Link Budget (dB) 12 Dispersion
Modem-e v2.x.x CHANGELOG
Modem-e v2.0.2 (2025-08-25)
Changes
[LfClock] Configuration: The LfClock configuration is no longer stored in flash memory. The recommended workaround for the transceiver is to set the
L 0.300 0.600 0.012 0.024 θ 0° 8° 0° 8° SG Micro Corp TX00033.000 www.sg-micro.com PACKAGE INFORMATION PACKAGE OUTLINE DIMENSIONS SOIC-8 0.6 D e 2.2 E1 E 5.2 b 1.27 RECOMMENDED LAND PATTERN (Unit: mm) L A A1 θ c A2 Dimensions Dimensions Symbol In Millimeters
Immunity to Environmental Conditions Test method Standard Test conditions Status EN 50155 section 12.2.3 (Column 2, Class TX) Temperature: -40℃ Cooling Test EN 60068-2-1 Dwell Time: 2 hrs/cycle No damage EN 50155 section 12.2.4 (Column 2, Class TX) Dry Heat Test EN 50155 section 12.2.4 (Column 3, Class TX & Column 4, Class TX)emperature: 70℃ / 85℃ PASS EN 60068-2-2 Duration: 6 hrs / 10min EN 50155 section 12.2.5 Temperature: 25℃~55℃ Damp Heat Test, Cyclic EN 60068-2-30 Humidity: 90%~100% RH PASS Duration
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