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PDF
RCDN9.pdf
) Alarm： Once alarm/Everyday alarm：One system each FM S/N ratio： Monaura：l 70dB Sleep： Sleep timer：Max. 90 minutes Stereo：70dB n nGeneral FM THD+N （1kHz） ：Monaura： l 0.4% Stereo：0.4% Power supply： (for E2)： AC 230 V, 50 Hz / 60Hz (for E1C)： AC 220V, 50Hz (for JP)： AC 100V, 50/60Hz Power consumption：
in „Hifi Kompaktanlage mit Bluetooth Sender ausstatten“ · Analoge Elektronik und Schaltungstechnik ·
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PDF
ATmega32.pdf
to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 33
in „STK500 als ISP“ · Mikrocontroller und Digitale Elektronik ·
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PDF
NT7533Lcd.pdf
(H=1). Caution As the programming range for the internally generated VLCD allows values above the max. allowed VLCD, the customer has to ensure while setting the VOP register and selecting the temperature compensation (TC), that under all conditions and including all tolerances the VLCD remains below
in „Seriell (4-Wire)-LCD-Ansteuerung mit NT7533“ · Mikrocontroller und Digitale Elektronik ·
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PDF
UM08001_JLinkARM.pdf
. KG 22 CHAPTER 1 Introduction Data input rise time (Trdi Max. 20ns Data input fall time (T ) Max. 20ns fdi Data output rise time (T rdo Max. 10ns Data output fall time (T ) fdo Max. 10ns Clock rise time (Trc) Max. 10ns Clock fall time (Tfc Max. 10ns Table 1.1
in „[V] J-Link JTAG Adapter USB für ARM abzugeben“ · Markt ·
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PDF
CAN-BootloaderPIC18F.pdf
communications with the CAN module through the serial port. For those who wish to experi- both CAN and RS-232 communications. Interfaces to ment with the interface, a total of 4 properties and 13 the CAN bus and programming data source are pro- vided by an external CAN transceiver and RS-232 methods are available
in „CAN-Bootloader für PIC18F“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Sp3A-DSP-1800A-Starter-Schematic-Rev1.pdf
_RHCLK6 N19 LED3 6 IO_L34n_1_RHCLK7 M26 FLASH_A10 IO_L35p_1_A10 M25 FLASH_A11 IO_L35n_1_A11 FPGA_RS232_Tx IO_L37p_1 P22 FPGA_RS232_Rx IO_L37n_1 N21 IO_L38p_1_A12 L24 FLASH_A12 IO_L38n_1_A13 M23 FLASH_A13 N18 FLASH_A14 IO_L39p_1_A14 N17 FLASH_A15 IO_L39n_1_A15 K25 IO_L41p_1 K26 DAC_VSYNC 13 +3.3V +3.3V
in „Schematics von Spartan 3A-DSP 1800 Board“ · FPGA, VHDL & Co. ·
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PDF
atmel-8393-mcu_wireless-atmega256rfr2-atmega128rfr2-atmega64rfr2_datasheet.pdf
address. 9.12.50 XAH_CTRL_0 – Transceiver Extended Operating Mode Control Register Bit 7 6 NA ($16C) MAX_FRAME_RETRIES3 MAX_FRAME_RETRIES2 XAH_CTRL_0 Read/Write RW RW Initial Value 0 0 Bit 5 4 NA ($16C) MAX_FRAME_RETRIES1 MAX_FRAME_RETRIES0 XAH_CTRL_0 Read/Write RW RW Initial Value 1 1 Bit 3 2 NA ($16C) MAX_CSMA_RETRIES2 MAX_CSMA_RETRIES1 XAH_CTRL_0 Read/Write RW RW Initial Value 1 0 Bit 1 0 NA ($16C) MAX_CSMA_RETRIES0 SLOTTED_OPERATION XAH_CTRL_0 Read/Write RW RW Initial Value 0 0 This register is used
in „AVR-Verlustleistung maximieren“ · Mikrocontroller und Digitale Elektronik ·
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PDF
HX8238A.pdf
) S957 BB6 (2) S958 BB5 (2) S959 BB4 (2) DUMMY (9) BB3 (2) G238 BB2 (2) G236 BB1 (2) G234 BB0 (2) G232 SDI (2) SCK (2) CSB (2) RESB (2) SDO (2) POL (1) QXH (1) DUMMY (1) TEST4 (1) TEST5 (1) TEST6 (1) TEST7 (1) TEST8 (1) TEST9 (1) TEST10 (1) TEST11 (1) TEST12 (1) TEST13 (1) TEST14 (1) TEST15 (1) G6 DUMMY
in „TFT- Ansteuerung ET0350G0DH6 (Glyn) mit HX8238 LCD Driver und Microchip Graphic Lib“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Mega32.pdf
to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 33
in „AVR Timer/Counter Zeit berechnen“ · Mikrocontroller und Digitale Elektronik ·
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PDF
AV02-0923EN-DS-ATF-55143-08Jun20120.pdf
100 DS I Gate Current [5] mA 1 GS P Total Power Dissipation [3] mW 270 diss P RF Input Power [5] in max. (Vds=2.7V, Ids=10mA) dBm 10 (Vds=0V, Ids=0mA) dBm 10 T ChannelTemperature °C 150 CH T StorageTemperature °C -65 to 150 STG Thermal Resistance [4] °C/W 235 jc ESD (Human Body Model) V 200 ESD (Machine
in „LNA Entwicklung von 10 MHZ bis 6 GHZ“ · Analoge Elektronik und Schaltungstechnik ·
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PDF
fla-203.pdf
LED3 +12V V7 -12V LED4 -12V V8 +12V Power supply unit G2 Output voltages Output voltage Min. load Max. load Comments +5V 3.0A 15.0A +12V 0.5A 5.0A -12V 0.0A 0.7A -5V 0.0A 0.3A not used Checking and setting Power supply unit G2 does not have any sensor lines to compensate the voltage drop through the
in „Kommunikation mit Leistungsprüfstand BOSCH FLA203“ · PC Hard- und Software ·
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PDF
ILI9325.pdf
4.5V ~ 6.0V VGH 10V ~ 20V 6 Liquid Crystal Drive VGL -5V ~ -15V Voltages VCL -1.9V ~ -3.0V VGH - VGL Max. 32V Vci - VCL Max. 6.0V DDVDH Vci1 x2 7 Internal Step-up Circuits VGH Vci1 x4, x5, x6 VGL Vci1 x-3, x-4, x-5 VCL Vci1 x-1 The information contained herein is the exclusive property of ILI Technology
in „Programmierung von ILI9325 TFT Display“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ILI9325DS_V0.35.pdf
4.5V ~ 6.0V VGH 10V ~ 20V 6 Liquid Crystal Drive VGL -5V ~ -15V Voltages VCL -1.9V ~ -3.0V VGH - VGL Max. 32V Vci - VCL Max. 6.0V DDVDH Vci1 x2 VGH Vci1 x4, x5, x6 7 Internal Step-up Circuits VGL Vci1 x-3, x-4, x-5 VCL Vci1 x-1 The information contained herein is the exclusive property of ILI Technology
in „[V]erkaufe TFT 2.8" und TFT 2.4" mit adapter PCB“ · Markt ·
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PDF
ILI9325DS_V0.28.pdf
4.5V ~ 6.0V VGH 10V ~ 20V 6 Liquid Crystal Drive VGL -5V ~ -15V Voltages VCL -1.9V ~ -3.0V VGH - VGL Max. 32V Vci - VCL Max. 6.0V DDVDH Vci1 x2 7 Internal Step-up Circuits VGH Vci1 x4, x5, x6 VGL Vci1 x-3, x-4, x-5 VCL Vci1 x-1 The information contained herein is the exclusive property of ILI Technology
in „Chinesisches TFT LCD zum Schnäppchenpreis“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Panasonic_JD_700_800_Series_Service_Manual_1_.pdf
voltage: 120V 'V±10% 220/240V'V ±10% • Input frequency: 50-60Hz • Output voltage/current: +12V/3.3A max. +SV/SA max. -12V/O.IA max. • Overall stability: ±S% or less 3 - 1 ~ JD·70n40 lAC 100Vl120V - ) TRANSFORMER TO FLOPPY UNIT1 TO FLOPPY UNIT2 w AC/DC DISTRIBUTION SBCTII (/-480424-0) (1-480424 -0) »c.
in „Heidenhain Monitor BE 212 für TNC 351“ · Analoge Elektronik und Schaltungstechnik ·
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PDF
Arcam-FMJ-P7.pdf
SUBPART J APPLICABLE AT THE DATE OF MANUFACTURE. COMPLY WITH DHHS RULE 21 CFR CAMBRIDGE, CB5 9PB. MAX WARNING: THIS APPLIANCE MUST BE EARTHED. Amplifier Board L924 Contents Circuit description Component overlay Parts list Circuit diagrams The line ‘NFB’ provides for a portion of the negative feedback
in „Bandbreite von analogen Audioschaltungen“ · Analoge Elektronik und Schaltungstechnik ·
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PDF
Arcam-FMJ-P7.pdf
SUBPART J APPLICABLE AT THE DATE OF MANUFACTURE. COMPLY WITH DHHS RULE 21 CFR CAMBRIDGE, CB5 9PB. MAX WARNING: THIS APPLIANCE MUST BE EARTHED. Amplifier Board L924 Contents Circuit description Component overlay Parts list Circuit diagrams The line ‘NFB’ provides for a portion of the negative feedback
in „Bester Audio OPV“ · Analoge Elektronik und Schaltungstechnik ·
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Datei
IntLib.txt
Module.IntLib AltiumLive\Converter\ZMDI_DC-DC_Converter\ZMDI DC-DC Converter.IntLib AltiumLive\CPLD\Altera_MAX_II\Altera MAX II.IntLib AltiumLive\CPLD\Altera_MAX_V\Altera MAX V.IntLib AltiumLive\CPLD\Atmel_CPLD_Industry_Compatible\Atmel CPLD Industry Compatible.IntLib AltiumLive\CPLD\Atmel_CPLD_Proprietary\Atmel
in „Altium 5.1.x Offline Libs“ · Mikrocontroller und Digitale Elektronik ·
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PDF
252039.pdf
coordinates exceed the maximum pattern size, the repeat, cramp or border color option is selected. S (max. ±8192) ) 9 8 max. 4096 pixels . a ( T Origin e p Texture 6 pattern 0 x a m 8.1.3 Frame buffer For drawing, the following area must be assigned to the Graphics Memory. The frame size (count of pixels
in „LCD Display / Controller eines Schweißgerätes prüfen“ · Mikrocontroller und Digitale Elektronik ·
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PDF
SANMOTION_R_M0006890N.pdf
cable to prevent water or oil from entering the motor. Seal with sheet-packing, etc. Cover Sag 50max 50max Water (oil) pool 2-5 2.Installation [Servo motor] Gear installation The oil level of the gear box should be below the oil seal lip, for a slight spraying effect on the lip. Create a hole
in „Servoregler/Servoverstärker Verständnislücke“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ILI9341_DS_V1.09.pdf
...................................................................................................232 19.3.1. Display Parallel 18/16/9/8-bit Interface Timing Characteristics (8080- Ⅰ system) ...........232 19.3.2. Display Parallel 18/16/9/8-bit Interface Timing Characteristics(8080- Ⅱ system) ......
in „Ansteuerung LCD ILI9341“ · Mikrocontroller und Digitale Elektronik ·
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PDF
EleLaDoku_V4.0.20B27.pdf
Integer Parameterwert Integer ValFloat Double Parameterwert Float ValText Varchar Parameterwert Text (Max 250 Zeichen) ValMemo Memo Parameterwert Memo (Max 64KB Text) AendDatum Timestamp Änderungsdatum Beschreibung der Parameter ParNr ParName Land ValInt ValFloat ValText ValMemo 1 DB-Version <Version Datenbank
in „EleLa - Elektronik Lagerverwaltung V4.0“ · Projekte & Code ·
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PDF
b2-guide166.pdf
The following examples show two means of doing this. The example in the left-hand diagram uses an RS232 link as might be connected via a MAX232 (or similar LT7011 etc.) to a PC. The 167’s bootstrap mode is entered by sending a null byte with one start and stop bit until the device replies with an acknowledge
in „Problem mit Infinion C167CR mit AM29F200B-70SE“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ST7735_128x160_SPI_Display.pdf
18-bits x 160) Display Colors (Color Mode) -7-bits for VCOM adjustment -Full Color: 262K, RGB=(666) max., Idle Mode OFF Wide Supply Voltage Range -I/O Voltage (VDDI to DGND): 1.65V~VDD -Color Reduce: 8-color, RGB=(111), Idle Mode ON (VDDI ≤ VDD) Programmable Pixel Color Format (Color Depth) for Various
in „ST7735 an MCU“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ssd1309.pdf
COM24 69 NC 149 SEG55 229 COM26 70 NC 150 SEG54 230 COM28 71 NC 151 SEG53 231 COM30 72 NC 152 SEG52 232 COM32 73 NC 153 SEG51 233 COM34 74 NC 154 SEG50 234 COM36 75 NC 155 SEG49 235 COM38 76 NC 156 SEG48 236 COM40 77 SEG127 157 SEG47 237 COM42 78 SEG126 158 SEG46 238 COM44 79 SEG125 159 SEG45 239 COM46
in „Display EA OLED L128-6“ · Mikrocontroller und Digitale Elektronik ·
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PDF
techb_mysmartusb-mk2_de_en.pdf
USB-UART-Bridge) 9 VCC für Board (schaltbar, maximale Belastung 9 VCC for board (switchable, be aware of max. load USB-Port beachten) of USB port) 10 Masse 10 ground 11-18 nicht benutzen 11-18 do not use 19 I C/TWI-Clock=SCL 19 IC/TWI-Clock=SCL 20 I C/TWI-Clock=SDA 20 IC/TWI-Clock=SDA 20 10 4 3 2 1 www.myAVR.de
in „Mikro brauch nach übertragen meistens noch einen Reset“ · Mikrocontroller und Digitale Elektronik ·
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Datei
main.c
eeprom_write_byte(&eeFooByte, nKeyPress); dauer = 0; Warte (100); } } } else{ bPortB = 1; } } return 0; int maxValue(int a[1998], int cnt) { int max; for(int i=0 ; i<cnt ; i++) { if(a[i] > a[i-1]) { 1998 = a[i]; } } return max; } int Array [1998]; Array [ 0 ] = 1999 ; Array [ 1 ] = 1998 ; Array [ 2 ] = 1997 ;
in „Geschwindigkeit durch Taster aus einem Array anwählen“ · Mikrocontroller und Digitale Elektronik ·
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PDF
AN10216.pdf
with the red stripe “Hi-Speed” 0.1 I C fitted above the standard USB logo. The reason to avoid RS-232 RS-423 use of the new spec version 2.0 as a generic name is 0.5 0 10 100 1000 that this version includes all the older versions and Backplane Length (meters) Cable Length (meters) speeds as well as
in „AVR TWI: Hängt nach dem Flaschen“ · Mikrocontroller und Digitale Elektronik ·
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PDF
SDS_Series_Oscilloscopes_Service_Manual_v1_0.pdf
Ground Input impedance 1MΩ±2%, in parallel with 10pF±5pF Probe attenuation factor 1X, 10X, 100X, 1000X Max. input voltage 400V (PK-PK) (DC + AC PK-PK) Input Bandwidth limit 20MHz, full bandwidth Channel –channel 50Hz: 100 : 1 isolation 10MHz: 40 : 1 Time delay between 150ps channel(typical) Horizontal SDS6062
in „WELEC W2000A vs. OWON SDS8102“ · Mikrocontroller und Digitale Elektronik ·
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PDF
xr20m1170.pdf
LIMITS L IMITS LIMITS LIMITS S YMBOL P ARAMETER 1.8V ± 5% 1.8V ± 10% 2.5V ± 10% 3.3V ± 10% UNIT M IN MAX MIN MAX M IN M AX M IN M AX XTAL1 UART Crystal Oscillator 24 24 24 24 MHz ECLK UART External Clock 32 24 50 64 MHz TECLK External Clock Time Period1ECLK 1ECLK 1/ECLK 1/ECLK ns FIGURE 20. C LOCK TIMING
in „UART XR20M1170: Register LCR läßt sich nicht ändern.“ · Mikrocontroller und Digitale Elektronik ·
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PDF
magnetic.pdf
which has two extreme values along the hysteresis curve Bx,1− B x,2 B x,1− B x,2 µmin = min , and µ max = max . (5.58) H x,1Hx,2H x,1− H x,2 Hx,1,Hx,2H x,1− H x,2 Hereµ min andµ max aretheminimumandmaximumslopeofthehysteresischaracteristics. The inequality µmin ≤ µ ≤ µ max (5.59) is obvious, from which
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PDF
ATMEGA8_DATENBLATT.pdf
to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT2 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 51
in „I2C/TWI TWBR > 10 warum?“ · Mikrocontroller und Digitale Elektronik ·
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PDF
802.3-2008_section2.pdf
IEEE. All rights reserved. 253 IEEE Std 802.3-2008 REVISION OF IEEE Std 802.3: Table 28–9—Timer min./max. value summary Parameter Min. Typ. Max. Units autoneg_wait_timer 500 1000 ms break_link_timer 1200 1500 ms data_detect_min_timer 15 47 µs data_detect_max_timer 78 100 µs flp_test_min_timer 5 25 µs flp_test_max_timer
in „Kommunikation uC mit PHY“ · Analoge Elektronik und Schaltungstechnik ·
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PDF
T100_Scaler.pdf
: 74h Size: 8 bits Table 3-213 Lock Count Bit Access Symbol Description [7:4] R/W locked_cnt_noisy_max These bits set the max value of the hlock sensor for noisy signals. 8 is added to this value. Default = 7 stands for 15. These bits set the max value of the hlock sensor for clean signals. 8 is [3:0] R/W locked_cnt_clean_max added to this value. Default = 4 stands for 12. 3.9.18 H Loop Max State Address Offset: 17h Access: Read/Write Default Value: CBh Size: 8 bits 83 电子专业技术主页： HTTP://WWW.LCDHOME.NET 资料收藏： 版权归原作者所有 谨供学习用
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PDF
db_atmega8.pdf
to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT2 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 51
in „ADC-Input und Auswahlverfahren“ · Mikrocontroller und Digitale Elektronik ·
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PDF
STC89C51RC-en.pdf
28 40 29 39 L 0θ H c Ge Y Seating Plane DIMENSIONS IN INCH DIMENSIONS IN SYMBOLS MILLMETERS MIN NOM MAX MIN NOM MAX A 0.165 - 0.180 4.191 - 4.572 A1 0.020 - - 0.508 - - A2 0.147 - 0.158 3.734 - 4.013 b1 0.026 0.028 0.032 0.660 0.711 0.813 b 0.013 0.017 0.021 0.330 0.432 0.533 c 0.007 0.010 0.0013 0.178
in „stc89c52rc programmieren“ · Mikrocontroller und Digitale Elektronik ·
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PDF
HAL_STM32F1.pdf
_7: Select max triangle amplitude of 7 – DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15 – DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31 – DAC_TRIANGLEAMPLITUDE_63: Select max triangle
in „CAN auf STM32F4“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ATtiny841_Datasheet.pdf
Flag Mode WGM02 WGM01 WGM00 Mode of Operation TOP OCRx at Set on(1) 0 0 0 0 Normal 0xFF Immediate MAX 1 0 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 0 1 0 CTC OCRA Immediate MAX 3 0 1 1 Fast PWM 0xFF BOTTOM MAX 4 1 0 0 Reserved – – – 5 1 0 1 PWM, Phase Correct OCRA TOP BOTTOM 6 1 1 0 Reserved – – – 7
in „TOCPMSA1 und TOCPMCOE Verhalten beim Attiny 841“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ATtiny441_841.pdf
Flag Mode WGM02 WGM01 WGM00 Mode of Operation TOP OCRx at Set on(1) 0 0 0 0 Normal 0xFF Immediate MAX 1 0 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 0 1 0 CTC OCRA Immediate MAX 3 0 1 1 Fast PWM 0xFF BOTTOM MAX 4 1 0 0 Reserved – – – 5 1 0 1 PWM, Phase Correct OCRA TOP BOTTOM 6 1 1 0 Reserved – – – 7
in „Suche nach ATtiny mit ADC und Gain > 20x“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ATtiny841_Datasheet.pdf
Flag Mode WGM02 WGM01 WGM00 Mode of Operation TOP OCRx at Set on(1) 0 0 0 0 Normal 0xFF Immediate MAX 1 0 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 0 1 0 CTC OCRA Immediate MAX 3 0 1 1 Fast PWM 0xFF BOTTOM MAX 4 1 0 0 Reserved – – – 5 1 0 1 PWM, Phase Correct OCRA TOP BOTTOM 6 1 1 0 Reserved – – – 7
in „sleep und Interrupt“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ATtiny841_Datasheet.pdf
Flag Mode WGM02 WGM01 WGM00 Mode of Operation TOP OCRx at Set on(1) 0 0 0 0 Normal 0xFF Immediate MAX 1 0 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 0 1 0 CTC OCRA Immediate MAX 3 0 1 1 Fast PWM 0xFF BOTTOM MAX 4 1 0 0 Reserved – – – 5 1 0 1 PWM, Phase Correct OCRA TOP BOTTOM 6 1 1 0 Reserved – – – 7
in „Takt-Vorskalierungsregister beim Attiny841“ · Mikrocontroller und Digitale Elektronik ·
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PDF
_ATmega32.pdf
to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 33
in „Anschwingvorgang µC & Quarz“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ATMega16.pdf
to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 33
in „DCF auf INT0“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Datasheet_ATmega1281_doc2549.pdf
TOM. There are two cases that give a transition without Compare Match. OCR0A changes its value from MAX, like in Figure 16-7. When the OCR0A value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond
in „LM73 über TWI/I2C mit Atmega1281 auslesen“ · Mikrocontroller und Digitale Elektronik ·
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PDF
AN332-1_Programming_Guide.pdf
LIATTEN[1:0] 0 0 LILEVEL[9:0] Bit Name Function 15:14 Reserved Always write to 0. Line Attenuation. 00 = Max input level = 190 mV ; input resistance = 3 k PK 13:12 LIATTEN[1:0] 01 = Max input level = 301 PK ; input resistance = 10 k 10 = Max input level = 416 PK ; input resistance = 4 k 11 = Max input
in „Si4705 und C8051F321 kommunizieren nicht“ · Mikrocontroller und Digitale Elektronik ·
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PDF
AVR_ATmega_328PB.pdf
set. The first figure below illustrates timing data for basic Timer/Counter operation close to the MAX value in all modes other than Phase Correct PWM mode. Figure 19-8 Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clI/O1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn The next figure shows the
in „ATmega328PB: UART(MC) empfängt falsche Daten“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Yaskawa-SGDB-xxADx-x-TSE-S800-16E.pdf
Apply the holding brake at the same time as the Servo ON. * 2 The mechanical contact takes 180 ms max. to be opened when the brake is turned ON and 100 ms max. to be closed when turned OFF. * 3 Allow 200 ms or more between the moment when the brake is turned ON and when the speed reference is input.
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PDF
S1D13513.pdf
Max Units BCLK Bus Clock Frequency 20 50 (Note 1,2) MHz fSDRAMCLK SDRAM Clock Frequency — 100 MHz f System Clock Frequency 20 50 MHz SYSCLK 1. The S1D13513 maximum Bus Clock frequency is 50MHz. However,
in „S1D113513 + AT91RM9200“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ATMega164_324_644_1284pa.pdf
TOM. There are two cases that give a transition without Compare Match. OCR0A changes its value from MAX, like in Figure 15-7. When the OCR0A value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond
in „Hilfe bei AD-Wandler!“ · Mikrocontroller und Digitale Elektronik ·
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PDF
TRW-24G.pdf
Conditions: VDD=+3V,VSS=0V,T =-40 cenAigrade to +85 centigrade Symbol Parameter(condition) Notes Min. Typ. Max. Units VDD Supply voltage 1.9 3.0 3.6 V TEMP Operating temperature -40 +27 +85 Centigrate fop Operting frequency 1) 2400 2524 MHz R GFSK Data rate direct mode 3) 250 1000 kbps FCHANNEL Channel spacing