1 | /************************************************************
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2 | * USI
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3 | ************************************************************/
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4 | #define __MSP430_HAS_USI__ /* Definition to show that Module is available */
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5 |
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6 |
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7 | SFR_8BIT(USICTL0); /* USI Control Register 0 */
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8 | SFR_8BIT(USICTL1); /* USI Control Register 1 */
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9 | SFR_8BIT(USICKCTL); /* USI Clock Control Register */
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10 | SFR_8BIT(USICNT); /* USI Bit Counter Register */
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11 | SFR_8BIT(USISRL); /* USI Low Byte Shift Register */
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12 | SFR_8BIT(USISRH); /* USI High Byte Shift Register */
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13 | SFR_16BIT(USICTL); /* USI Control Register */
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14 | SFR_16BIT(USICCTL); /* USI Clock and Counter Control Register */
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15 | SFR_16BIT(USISR); /* USI Shift Register */
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16 |
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17 |
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18 | #define USIPE7 (0x80) /* USI Port Enable Px.7 */
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19 | #define USIPE6 (0x40) /* USI Port Enable Px.6 */
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20 | #define USIPE5 (0x20) /* USI Port Enable Px.5 */
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21 | #define USILSB (0x10) /* USI LSB first 1:LSB / 0:MSB */
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22 | #define USIMST (0x08) /* USI Master Select 0:Slave / 1:Master */
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23 | #define USIGE (0x04) /* USI General Output Enable Latch */
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24 | #define USIOE (0x02) /* USI Output Enable */
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25 | #define USISWRST (0x01) /* USI Software Reset */
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26 |
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27 |
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28 | #define USICKPH (0x80) /* USI Sync. Mode: Clock Phase */
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29 | #define USII2C (0x40) /* USI I2C Mode */
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30 | #define USISTTIE (0x20) /* USI START Condition interrupt enable */
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31 | #define USIIE (0x10) /* USI Counter Interrupt enable */
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32 | #define USIAL (0x08) /* USI Arbitration Lost */
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33 | #define USISTP (0x04) /* USI STOP Condition received */
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34 | #define USISTTIFG (0x02) /* USI START Condition interrupt Flag */
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35 | #define USIIFG (0x01) /* USI Counter Interrupt Flag */
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36 |
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37 |
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38 | #define USIDIV2 (0x80) /* USI Clock Divider 2 */
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39 | #define USIDIV1 (0x40) /* USI Clock Divider 1 */
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40 | #define USIDIV0 (0x20) /* USI Clock Divider 0 */
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41 | #define USISSEL2 (0x10) /* USI Clock Source Select 2 */
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42 | #define USISSEL1 (0x08) /* USI Clock Source Select 1 */
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43 | #define USISSEL0 (0x04) /* USI Clock Source Select 0 */
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44 | #define USICKPL (0x02) /* USI Clock Polarity 0:Inactive=Low / 1:Inactive=High */
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45 | #define USISWCLK (0x01) /* USI Software Clock */
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46 |
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47 |
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48 | #define USIDIV_0 (0x00) /* USI Clock Divider: 0 */
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49 | #define USIDIV_1 (0x20) /* USI Clock Divider: 1 */
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50 | #define USIDIV_2 (0x40) /* USI Clock Divider: 2 */
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51 | #define USIDIV_3 (0x60) /* USI Clock Divider: 3 */
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52 | #define USIDIV_4 (0x80) /* USI Clock Divider: 4 */
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53 | #define USIDIV_5 (0xA0) /* USI Clock Divider: 5 */
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54 | #define USIDIV_6 (0xC0) /* USI Clock Divider: 6 */
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55 | #define USIDIV_7 (0xE0) /* USI Clock Divider: 7 */
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56 |
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57 |
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58 | #define USISSEL_0 (0x00) /* USI Clock Source: 0 */
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59 | #define USISSEL_1 (0x04) /* USI Clock Source: 1 */
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60 | #define USISSEL_2 (0x08) /* USI Clock Source: 2 */
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61 | #define USISSEL_3 (0x0C) /* USI Clock Source: 3 */
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62 | #define USISSEL_4 (0x10) /* USI Clock Source: 4 */
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63 | #define USISSEL_5 (0x14) /* USI Clock Source: 5 */
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64 | #define USISSEL_6 (0x18) /* USI Clock Source: 6 */
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65 | #define USISSEL_7 (0x1C) /* USI Clock Source: 7 */
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66 |
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67 |
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68 | #define USISCLREL (0x80) /* USI SCL Released */
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69 | #define USI16B (0x40) /* USI 16 Bit Shift Register Enable */
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70 | #define USIIFGCC (0x20) /* USI Interrupt Flag Clear Control */
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71 | #define USICNT4 (0x10) /* USI Bit Count 4 */
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72 | #define USICNT3 (0x08) /* USI Bit Count 3 */
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73 | #define USICNT2 (0x04) /* USI Bit Count 2 */
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74 | #define USICNT1 (0x02) /* USI Bit Count 1 */
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75 | #define USICNT0 (0x01) /* USI Bit Count 0 */
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76 | /************************************************************
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