Hallo, guten Tag. Ich kann mit dem Programm unten Daten(Byte) empfangen die dann in das RAM geschrieben werden. Klappt wunderbar. Beim Senden wird beanstandet das ich "speicher_ram" benutze im Process darunter: Die Fehlermeldung: Error (10028): Can't resolve multiple constant drivers for net "RamAddr[7]" at ram_rs232.vhd(52) Error (10029): Constant driver at ram_rs232.vhd(43) Error (10028): Can't resolve multiple constant drivers for net "RamAddr[6]" at ram_rs232.vhd(52) Error (10028): Can't resolve multiple constant drivers for net "RamAddr[5]" at ram_rs232.vhd(52) Error (10028): Can't resolve multiple constant drivers for net "RamAddr[4]" at ram_rs232.vhd(52) Error (10028): Can't resolve multiple constant drivers for net "RamAddr[3]" at ram_rs232.vhd(52) Error (10028): Can't resolve multiple constant drivers for net "RamAddr[2]" at ram_rs232.vhd(52) Error (10028): Can't resolve multiple constant drivers for net "RamAddr[1]" at ram_rs232.vhd(52) Error (10028): Can't resolve multiple constant drivers for net "RamAddr[0]" at ram_rs232.vhd(52) Dieses wird beanstanded nach dem ich es eingebaut hatte: ----------------------------------------------------------- process(clk) begin if rising_edge(clk) then if (c<9000000 ) then c <= c+1; Tx_Start <= '0'; else c <= 0; if (RamAddr < 100) and (sw(1) = '1') then RamAddr <= RamAddr + 1; TX_Data <= speicher_ram(RamAddr); Tx_Start <= '1'; end if; end if; end if; end process; ------------------------------------------------------
1 | library IEEE; |
2 | use IEEE.STD_LOGIC_1164.ALL; |
3 | use IEEE.NUMERIC_STD.ALL; |
4 | |
5 | entity ram_rs232 is |
6 | Generic ( Quarz_Taktfrequenz : integer := 50000000; |
7 | Baudrate : integer := 9600 |
8 | );
|
9 | port( |
10 | clk : in std_logic; |
11 | led_g : out std_logic_vector(7 downto 0); |
12 | sw : in std_logic_vector(1 downto 0); |
13 | RXD : in STD_LOGIC; |
14 | TXD : out STD_LOGIC |
15 | );
|
16 | end ram_rs232; |
17 | |
18 | architecture Behavioral of ram_rs232 is |
19 | |
20 | Type ram is ARRAY (0 to 127) OF std_logic_vector(7 downto 0); |
21 | signal speicher_ram : ram; |
22 | signal RamAddr : integer range 0 to 128 := 0; |
23 | |
24 | signal RX_Data : STD_LOGIC_VECTOR (7 downto 0); |
25 | signal rxd_sr : std_logic_vector (3 downto 0) := "1111"; |
26 | signal rxsr : std_logic_vector (7 downto 0) := "00000000"; |
27 | signal rxbitcnt: integer range 0 to 9 := 9; |
28 | signal rxcnt : integer range 0 to (Quarz_Taktfrequenz/Baudrate)-1; |
29 | |
30 | signal TX_Data : STD_LOGIC_VECTOR (7 downto 0); |
31 | signal txstart : std_logic := '0'; |
32 | signal txsr : std_logic_vector (9 downto 0) := "1111111111"; |
33 | signal txbitcnt : integer range 0 to 10 := 10; |
34 | signal txcnt : integer range 0 to (Quarz_Taktfrequenz/Baudrate)-1; |
35 | signal TX_Start : STD_LOGIC; |
36 | |
37 | signal c : integer range 0 to 10000000 := 0; |
38 | |
39 | begin
|
40 | |
41 | process(clk) |
42 | begin
|
43 | if rising_edge(clk) then |
44 | if sw(0) = '1' then |
45 | RamAddr <= 0; |
46 | end if; |
47 | end if; |
48 | end process; |
49 | |
50 | process(clk) |
51 | begin
|
52 | if rising_edge(clk) then |
53 | if (c<9000000 ) then |
54 | c <= c+1; |
55 | Tx_Start <= '0'; |
56 | else
|
57 | c <= 0; |
58 | if (RamAddr < 100) and (sw(1) = '1') then |
59 | RamAddr <= RamAddr + 1; |
60 | TX_Data <= speicher_ram(RamAddr); |
61 | Tx_Start <= '1'; |
62 | end if; |
63 | end if; |
64 | end if; |
65 | end process; |
66 | |
67 | process(clk) |
68 | begin
|
69 | if rising_edge(clk) then |
70 | if RX_Data > "00000000" then |
71 | RamAddr <= RamAddr + 1; |
72 | speicher_ram(RamAddr) <= RX_Data; |
73 | led_g <= RX_Data; |
74 | end if; |
75 | end if; |
76 | end process; |
77 | |
78 | process(clk) |
79 | begin
|
80 | if rising_edge(clk) then |
81 | txstart <= TX_Start; |
82 | if (TX_Start='1' and txstart='0') then |
83 | txcnt <= 0; |
84 | txbitcnt <= 0; |
85 | txsr <= '1' & TX_Data & '0'; |
86 | else
|
87 | if(txcnt<(Quarz_Taktfrequenz/Baudrate)-1) then |
88 | txcnt <= txcnt+1; |
89 | else
|
90 | if (txbitcnt<10) then |
91 | txcnt <= 0; |
92 | txbitcnt <= txbitcnt+1; |
93 | txsr <= '1' & txsr(txsr'left downto 1); |
94 | end if; |
95 | end if; |
96 | end if; |
97 | end if; |
98 | end process; |
99 | |
100 | process(clk) |
101 | begin
|
102 | if rising_edge(clk) then |
103 | rxd_sr <= rxd_sr(rxd_sr'left-1 downto 0) & RXD; |
104 | if (rxbitcnt<9) then |
105 | if(rxcnt<(Quarz_Taktfrequenz/Baudrate)-1) then |
106 | rxcnt <= rxcnt+1; |
107 | else
|
108 | rxcnt <= 0; |
109 | rxbitcnt <= rxbitcnt+1; |
110 | rxsr <= rxd_sr(rxd_sr'left-1) & rxsr(rxsr'left downto 1); |
111 | end if; |
112 | else
|
113 | if (rxd_sr(3 downto 2) = "10") then |
114 | rxcnt <= ((Quarz_Taktfrequenz/Baudrate)-1)/2; |
115 | rxbitcnt <= 0; |
116 | end if; |
117 | end if; |
118 | end if; |
119 | end process; |
120 | |
121 | TXD <= txsr(0); |
122 | RX_Data <= rxsr; |
123 | |
124 | end Behavioral; |
Danke. Gruss