1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 | use IEEE.std_logic_arith.all;
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4 |
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5 |
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6 |
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7 |
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8 | entity PID_Regler is
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9 | generic(
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10 | data_width: integer:= 14;
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11 | intern_data_width: integer:= 28;
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12 | TA: integer:=1
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13 | );
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14 | port (
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15 | w : in std_logic_vector(data_width-1 downto 0); --:= (others => '0');
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16 | x : in std_logic_vector(data_width-1 downto 0); --:= (others => '0');
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17 | y : out std_logic_vector(data_width-1 downto 0); --:= (others => '0');
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18 | TP : in std_logic_vector(intern_data_width-1 downto 0);
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19 | TI : in std_logic_vector(intern_data_width-1 downto 0);
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20 | TD : in std_logic_vector(intern_data_width-1 downto 0);
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21 | clk_i : in std_logic;
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22 | rst_i : in std_logic
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23 | );
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24 | end PID_Regler;
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25 |
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26 | architecture Behavioral of PID_Regler is
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27 |
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28 | signal e1 : std_logic_vector(data_width-1 downto 0) := (others => '0');
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29 | signal ealt : std_logic_vector(data_width-1 downto 0) := (others => '0');
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30 | signal e2 : std_logic_vector(data_width-1 downto 0) := (others => '0');
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31 | signal e3 : std_logic_vector(data_width-1 downto 0) := (others => '0');
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32 |
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33 | begin
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34 |
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35 | Regler1: process(clk_i, rst_i)
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36 | --rst_i wurde hinzugefügt
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37 | variable yp: std_logic_vector(intern_data_width-1 downto 0);
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38 | variable yi: std_logic_vector(intern_data_width-1 downto 0);
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39 | variable yi_alt: std_logic_vector(intern_data_width-1 downto 0);
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40 | variable yd: std_logic_vector(intern_data_width-1 downto 0);
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41 |
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42 | begin
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43 | if (rst_i = '1') then
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44 | yp := (others => '0');
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45 | yi := (others => '0');
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46 | yi_alt:=(others => '0');
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47 | yd := (others => '0');
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48 | y <= (others => '0');
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49 | elsif (clk_i='1') then
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50 | e1 <= std_logic_vector(signed(w) - signed(x));
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51 | yp := (signed(TP)*signed(e1));
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52 | yi := yi_alt+(TI*e1*TA); -- yi_alt=yi
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53 | yd := (TD*((e1-ealt)/TA)); -- ealt=e
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54 | ealt <= e1;
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55 | y <= (yp+yi+yd);
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56 |
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57 | yi_alt := yi;
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58 | end if;
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59 | end process Regler1;
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60 |
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61 |
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62 |
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63 | Regler2: process(clk_i, rst_i)
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64 | --rst_i wurde hinzugefügt
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65 | variable yp: std_logic_vector(intern_data_width-1 downto 0);
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66 | variable yi: std_logic_vector(intern_data_width-1 downto 0);
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67 | variable yi_alt: std_logic_vector(intern_data_width-1 downto 0);
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68 | variable yd: std_logic_vector(intern_data_width-1 downto 0);
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69 |
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70 | begin
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71 | if (rst_i = '1') then
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72 | yp := (others => '0');
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73 | yi := (others => '0');
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74 | yd := (others => '0');
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75 | ealt <= (others => '0');
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76 | y <= (others => '0');
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77 | elsif (clk_i='1') then
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78 | e2 <= std_logic_vector(signed(w) - signed(x));
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79 | yp := ((TP)*(e2));
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80 | yi := ((yi_alt)+((TI)*(e2)*TA)); -- yi_alt=yi
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81 | yd := ((TD)*(((e2)-(ealt))/TA)); -- ealt=e
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82 | ealt <= e2;
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83 | y <= ((yp)+(yi)+(yd));
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84 |
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85 | yi_alt := yi;
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86 | end if;
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87 | end process Regler2;
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88 |
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89 |
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90 | Regler3: process(clk_i, rst_i)
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91 | --rst_i wurde hinzugefügt
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92 | variable yp: std_logic_vector(intern_data_width-1 downto 0);
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93 | variable yi: std_logic_vector(intern_data_width-1 downto 0);
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94 | variable yi_alt: std_logic_vector(intern_data_width-1 downto 0);
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95 | variable yd: std_logic_vector(intern_data_width-1 downto 0);
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96 |
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97 | begin
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98 | if (rst_i = '1') then
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99 | yp := (others => '0');
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100 | yi := (others => '0');
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101 | yd := (others => '0');
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102 | y <= (others => '0');
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103 | elsif(clk_i='1') then
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104 | e3 <= std_logic_vector(signed(w) - signed(x));
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105 | yp := ((TP)*e3);
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106 | yi := ((yi_alt)+((TI)*(e3)*TA)); -- yi_alt=yi
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107 | yd := ((TD)*(((e3)-(ealt))/TA)); -- ealt=e
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108 | ealt <= (e3);
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109 | y <= ((yp)+(yi)+(yd));
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110 |
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111 | yi_alt := yi;
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112 | end if;
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113 | end process Regler3;
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114 | end Behavioral;
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115 |
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116 | •
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