1 | library ieee;
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2 | use ieee.std_logic_1164.all;
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3 | use ieee.std_logic_unsigned.all;
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4 | use ieee.numeric_std.all;
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5 |
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6 | entity lfsr_counter is
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7 | generic(
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8 | WIDTH : integer := 10
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9 | );
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10 | port(
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11 | clk : in std_logic; --clock
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12 | rst : in std_logic; --positiv rst
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13 | lfsr_out : out std_logic --1 bit output of lfsr
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14 | );
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15 | end lfsr_counter;
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16 |
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17 | -------------------------------------------------------------------
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18 |
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19 | architecture behavioral of lfsr_counter is
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20 | type state_type is (state_rst, state_go); --rst: reset; go: lfsr shifts
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21 |
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22 | signal present_state : state_type;
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23 | signal next_state : state_type;
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24 | signal lfsr : std_logic_vector((WIDTH - 1) downto 0) := (others => '0');
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25 | signal d0 : std_logic := '0'; --stores the current feedbackvalue
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26 |
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27 | begin
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28 |
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29 | --sequencial logic:
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30 | -------------------------------------------------------------------
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31 | state_register : process(clk, rst)
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32 | begin
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33 | if (rst = '1') then
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34 | present_state <= state_rst; --default state on reset.
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35 | elsif (rising_edge(clk)) then
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36 | present_state <= next_state; --state change
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37 | end if;
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38 | end process;
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39 |
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40 | -- combinatorial logic
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41 | -------------------------------------------------------------------
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42 |
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43 | comb_logic : process(present_state, rst)
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44 | begin
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45 | case present_state is
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46 | when state_rst =>
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47 | if (rst = '1') then
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48 | next_state <= state_rst;
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49 | else
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50 | next_state <= state_go;
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51 | end if;
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52 | when state_go =>
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53 | if (rst = '1') then
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54 | next_state <= state_rst;
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55 | else
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56 | next_state <= state_go;
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57 | end if;
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58 | end case;
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59 | end process;
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60 |
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61 | output_logic : process(present_state)
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62 | begin
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63 | if (present_state = state_go) then
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64 | --assert ((WIDTH >= 3) and (WIDTH <= 10))
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65 | --report "Error: the LFSR width must be between 3 and 10" severity failure;
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66 | case WIDTH is --definitions for the feedback
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67 | when 3 => d0 <= lfsr(2) xnor lfsr(1);
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68 | when 4 => d0 <= lfsr(3) xnor lfsr(2);
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69 | when 5 => d0 <= lfsr(4) xnor lfsr(2);
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70 | when 6 => d0 <= lfsr(5) xnor lfsr(4);
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71 | when 7 => d0 <= lfsr(6) xnor lfsr(5);
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72 | when 8 => d0 <= lfsr(7) xnor lfsr(5) xnor lfsr(4) xnor lfsr(3);
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73 | when 9 => d0 <= lfsr(8) xnor lfsr(4);
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74 | when 10 => d0 <= lfsr(9) xnor lfsr(6);
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75 | when others => null;
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76 | end case;
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77 | lfsr <= std_logic_vector(unsigned(lfsr) sll 1); --shifting all bits to left by 1
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78 | lfsr_out <= lfsr(WIDTH - 1); --MSB to output
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79 | lfsr <= lfsr(WIDTH - 1 downto 1) & d0; --concatenate the feedback to the lfsr
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80 | else
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81 | lfsr <= (others => '0'); --reset state -> lfsr contains only '0'
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82 | lfsr_out <= '0';
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83 | end if;
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84 | end process;
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85 | end architecture;
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