Es soll eine 10bit Binärzahl in eine 4 Stellen BCD gewandelt. Weil ich LUTs sparen will und FPGAs so schnell sind, hier mal ein Etwas anderer Ansatz: Einfach BCD-Counter schnell bis zum gewünschten Anzeigewert hochzählen ( wie beim alten Autotacho ). Was haltet Ihr von der Version unter VHDL-Gesichtspunkten?
1 | LIBRARY ieee; |
2 | USE ieee.std_logic_1164.all; |
3 | USE ieee.numeric_std.all; |
4 | |
5 | entity bin2bcd is |
6 | port( |
7 | sysClk: in std_logic; |
8 | data: in std_logic_vector ( 9 downto 0 ); |
9 | start: in std_logic; |
10 | |
11 | digit0: out std_logic_vector ( 3 downto 0 ); |
12 | digit1: out std_logic_vector ( 3 downto 0 ); |
13 | digit2: out std_logic_vector ( 3 downto 0 ); |
14 | digit3Bit: out std_logic; |
15 | |
16 | ready: out std_logic:='0' |
17 | );
|
18 | end entity bin2bcd; |
19 | |
20 | architecture rtl of bin2bcd is |
21 | signal counter: integer range 0 to 1023:=0; |
22 | signal dig0: integer range 0 to 9:=0; |
23 | signal dig1: integer range 0 to 9:=0; |
24 | signal dig2: integer range 0 to 9:=0; |
25 | signal dig3Bit: std_logic := '0'; |
26 | begin
|
27 | process begin |
28 | wait until rising_edge(sysClk); |
29 | if(start='1') then |
30 | counter<=to_integer(unsigned(data)); |
31 | digit0 <= x"0"; |
32 | digit1 <= x"0"; |
33 | digit2 <= x"0"; |
34 | digit3Bit<='0'; |
35 | else
|
36 | if(counter>0) then |
37 | ready<='0'; |
38 | -- digit 0 --
|
39 | if(dig0<9) then |
40 | dig0<=dig0+1; |
41 | else
|
42 | dig0<=0; |
43 | -- digit 1 --
|
44 | if(dig1<9)then |
45 | dig1<=dig1+1; |
46 | else
|
47 | dig1<=0; |
48 | |
49 | -- digit 2 + digit3Bit---
|
50 | if(dig2<9)then |
51 | dig2<=dig2+1; |
52 | else
|
53 | dig2<=0; |
54 | dig3Bit<='1'; |
55 | end if; |
56 | end if; |
57 | |
58 | end if; |
59 | |
60 | counter<=counter-1; |
61 | |
62 | else
|
63 | ready<='1'; |
64 | digit0 <= std_logic_vector(to_unsigned(dig0,4)); |
65 | digit1 <= std_logic_vector(to_unsigned(dig1,4)); |
66 | digit2 <= std_logic_vector(to_unsigned(dig2,4)); |
67 | digit3Bit <= dig3Bit; |
68 | |
69 | end if; |
70 | end if; |
71 | end process; |
72 | |
73 | |
74 | end architecture; |