Simulation digitaler Rauschgenerator

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity noise_bit_gen is

  Generic (  n_invChain_osc1 : integer := 8; 

        n_invChain_osc2 : integer := 12); 

    Port (   rst : in std_logic; 

        output : out std_logic);

end noise_bit_gen;

-- Quelle: 

-- https://www.mikrocontroller.net/articles/Digitaler_Rauschgenerator_im_FPGA

architecture Behavioral of noise_bit_gen is

  constant k1 : integer := 13; 

  constant k2 : integer := 27; 

  constant n_invChain_secondBlock : integer := 4; 

  signal cnt1 : integer range 0 to k1 := 0; 

  signal cnt2 : integer range 0 to k2 := 0; 

  signal invChain_osc1 : std_logic_vector(n_invChain_osc1 - 1 downto 0) := (others => '0'); 

  signal invChain_osc2 : std_logic_vector(n_invChain_osc2 - 1 downto 0) := (others => '0'); 

  signal invChain_secondBlock_1 : std_logic_vector(n_invChain_secondBlock - 1 downto 0) := (others => '0'); 

  signal invChain_secondBlock_2 : std_logic_vector(n_invChain_secondBlock - 1 downto 0) := (others => '0'); 

  signal mux1_out : std_logic := '0'; 

  signal mux2_out : std_logic := '0'; 

  signal short_feedback_osc1 : std_logic := '0'; 

  signal short_feedback_osc2 : std_logic := '0'; 

  attribute dont_touch : string;

  attribute dont_touch of cnt1 : signal is "true";

  attribute dont_touch of cnt2 : signal is "true";

  attribute dont_touch of invChain_osc1 : signal is "true";

  attribute dont_touch of invChain_osc2 : signal is "true";

  attribute dont_touch of invChain_secondBlock_1 : signal is "true";

  attribute dont_touch of invChain_secondBlock_2 : signal is "true";

  attribute dont_touch of mux1_out : signal is "true";

  attribute dont_touch of mux2_out : signal is "true";

  attribute dont_touch of short_feedback_osc1 : signal is "true";

  attribute dont_touch of short_feedback_osc2 : signal is "true";

begin

  ----------------------------------------------------------------------------

  -- OSC 1 

  -- inverter chain OSC1

  invChain_osc1(0) <= not(mux2_out) when (rst = '0') else '0'; 

  invChain_osc1(1) <= not(invChain_osc1(0)) when (rst = '0') else '0'; 

  invChain_osc1(2) <= not(invChain_osc1(1)) when (rst = '0') else '0'; 

  invChain_osc1(3) <= not(invChain_osc1(2)) when (rst = '0') else '0'; 

  invChain_osc1(4) <= not(invChain_osc1(3)) when (rst = '0') else '0'; 

  invChain_osc1(5) <= not(invChain_osc1(4)) when (rst = '0') else '0'; 

  invChain_osc1(6) <= not(invChain_osc1(5)) when (rst = '0') else '0'; 

  invChain_osc1(7) <= not(invChain_osc1(6)) when (rst = '0') else '0'; 

  -- signle inverter

  short_feedback_osc1 <= not(invChain_osc1(invChain_osc1'left)) when (rst = '0') else '0'; 

  -- inverter chain OSC1 second block 

  invChain_secondBlock_1(0) <= not(short_feedback_osc1) when (rst = '0') else '0'; 

  invChain_secondBlock_1(1) <= not(invChain_secondBlock_1(0)) when (rst = '0') else '0'; 

  invChain_secondBlock_1(2) <= not(invChain_secondBlock_1(1)) when (rst = '0') else '0'; 

  invChain_secondBlock_1(3) <= not(invChain_secondBlock_1(2)) when (rst = '0') else '0'; 

  -- counter for OSC1 

  process 

  begin 

    wait until rising_edge(invChain_osc1(invChain_osc1'left)); 

    if cnt1 < k1 then 

      cnt1 <= cnt1 + 1; 

    else 

      cnt1 <= 0; 

    end if; 

  end process; 

  -- comparator and multiplexer 

  mux1_out <= short_feedback_osc1 when (cnt1 < (k1/2)) else

        invChain_secondBlock_1(3); 

  ----------------------------------------------------------------------------

  ----------------------------------------------------------------------------

  ----------------------------------------------------------------------------

  -- OSC 2 

  -- inverter chain OSC1

  invChain_osc2(0) <= not(mux1_out) when (rst = '0') else '0';

  invChain_osc2(1) <= not(invChain_osc2(0)) when (rst = '0') else '0'; 

  invChain_osc2(2) <= not(invChain_osc2(1)) when (rst = '0') else '0'; 

  invChain_osc2(3) <= not(invChain_osc2(2)) when (rst = '0') else '0'; 

  invChain_osc2(4) <= not(invChain_osc2(3)) when (rst = '0') else '0'; 

  invChain_osc2(5) <= not(invChain_osc2(4)) when (rst = '0') else '0'; 

  invChain_osc2(6) <= not(invChain_osc2(5)) when (rst = '0') else '0'; 

  invChain_osc2(7) <= not(invChain_osc2(6)) when (rst = '0') else '0'; 

  invChain_osc2(8) <= not(invChain_osc2(7)) when (rst = '0') else '0'; 

  invChain_osc2(9) <= not(invChain_osc2(8)) when (rst = '0') else '0'; 

  invChain_osc2(10) <= not(invChain_osc2(9)) when (rst = '0') else '0'; 

  invChain_osc2(11) <= not(invChain_osc2(10)) when (rst = '0') else '0'; 

  -- signle inverter

  short_feedback_osc2 <= not(invChain_osc2(invChain_osc2'left)) when (rst = '0') else '0'; 

  -- inverter chain OSC1 second block 

  invChain_secondBlock_2(0) <= not(short_feedback_osc2) when (rst = '0') else '0'; 

  invChain_secondBlock_2(1) <= not(invChain_secondBlock_2(0)) when (rst = '0') else '0'; 

  invChain_secondBlock_2(2) <= not(invChain_secondBlock_2(1)) when (rst = '0') else '0'; 

  invChain_secondBlock_2(3) <= not(invChain_secondBlock_2(2)) when (rst = '0') else '0'; 

  -- counter for OSC1 

  process 

  begin 

    wait until rising_edge(invChain_osc2(invChain_osc2'left)); 

    if cnt2 < k2 then 

      cnt2 <= cnt2 + 1; 

    else 

      cnt2 <= 0; 

    end if; 

  end process; 

  -- comparator and multiplexer 

  mux2_out <= short_feedback_osc2 when (cnt2 < (k2/2)) else

        invChain_secondBlock_2(3); 

  ----------------------------------------------------------------------------

  ----------------------------------------------------------------------------

  ----------------------------------------------------------------------------

  -- output 

  output <= invChain_osc1(invChain_osc1'left) XOR invChain_osc2(invChain_osc2'left); 

  ----------------------------------------------------------------------------

  ----------------------------------------------------------------------------

end Behavioral;