1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 | use work.utilities.all;
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4 |
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5 | -- Uncomment the following library declaration if using
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6 | -- arithmetic functions with Signed or Unsigned values
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7 | use IEEE.NUMERIC_STD.ALL;
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8 |
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9 | -- Uncomment the following library declaration if instantiating
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10 | -- any Xilinx leaf cells in this code.
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11 | --library UNISIM;
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12 | --use UNISIM.VComponents.all;
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13 |
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14 | entity VGA_Controller is
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15 | Port ( red : out STD_LOGIC_VECTOR (3 downto 0);
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16 | grn : out STD_LOGIC_VECTOR (3 downto 0);
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17 | blu : out STD_LOGIC_VECTOR (3 downto 0);
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18 | vsync : out STD_LOGIC;
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19 | hsync : out STD_LOGIC;
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20 |
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21 | clk : in STD_LOGIC);
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22 | end VGA_Controller;
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23 |
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24 | architecture Behavioral of VGA_Controller is
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25 | signal int_vsync : STD_LOGIC; -- Triggert 2. Timer für Signalverlängerung
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26 | signal int_hsync : STD_LOGIC; -- Triggert 2. Timer für Signalverlängerung
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27 | signal start_vsync : std_logic;
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28 | signal start_hsync : std_logic;
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29 | signal end_vsync : std_logic;
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30 | signal end_hsync : std_logic;
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31 | signal rst_vsync : std_logic;
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32 | signal rst_hsync : std_logic;
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33 | signal vsync_count : std_logic_vector(log2(1678400)-1 downto 0);
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34 | signal hsync_count : std_logic_vector(log2(3177)-1 downto 0);
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35 | begin
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36 |
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37 | process (clk)
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38 | begin
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39 | if rising_edge(clk) then
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40 | if hsync_count <= x"236" or hsync_count >= x"C0B" or vsync_count >= ('1' & x"8EC78") or vsync_count <= ('0' & x"1A770") then
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41 | red <= "0000";
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42 | blu <= "0000";
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43 | grn <= "0000";
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44 | else
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45 | red <= "1111";
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46 | blu <= "1111";
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47 | grn <= "1111";
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48 | end if;
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49 | end if;
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50 | end process;
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51 |
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52 | process (clk)
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53 | begin
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54 | if rising_edge(clk) then
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55 | if hsync_count <= x"04D" then --x"fe4d90" then
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56 | hsync <= '0'; --Signal ausgeben
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57 | else
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58 | hsync <= '1';
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59 | end if;
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60 | end if;
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61 | end process;
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62 |
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63 | h_sync: entity work.Counter
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64 | generic map (
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65 | MAX => 3177,
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66 | MIN => log2(3177-1)
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67 | )
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68 | port map(
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69 | d_in => x"04E", --: in std_logic_vector(log2(MAX)-1 downto 0),
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70 | load => int_vsync, --: in std_logic,
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71 | up => '1', --: in std_logic := '1',
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72 | en => '1', --: in std_logic,
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73 | rst => '0', --: in std_logic,
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74 | clk => clk, --: in std_logic,
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75 | ov => int_hsync,
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76 | count => hsync_count --: out std_logic_vector(log2(MAX)-1 downto 0)
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77 | );
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78 |
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79 | process (clk)
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80 | begin
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81 | if rising_edge(clk) then
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82 | if vsync_count <= '0' & x"00960" then --x"AFC8" then
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83 | vsync <= '0'; --Signal ausgeben
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84 | else
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85 | vsync <= '1';
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86 | end if;
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87 | end if;
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88 | end process;
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89 |
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90 | v_sync: entity work.Counter
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91 | generic map (
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92 | MAX => 1678400-1,
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93 | MIN => log2(1678400-1)
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94 | )
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95 | port map(
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96 | d_in => (others => '0'), --: in std_logic_vector(log2(MAX)-1 downto 0),
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97 | load => '0', --: in std_logic,
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98 | up => '1', --: in std_logic := '1',
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99 | en => '1', --: in std_logic,
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100 | rst => '0', --: in std_logic,
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101 | clk => clk, --: in std_logic,
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102 | ov => int_vsync,
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103 | count => vsync_count --: out std_logic_vector(log2(MAX)-1 downto 0)
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104 | );
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105 | end Behavioral;
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