1 | /*
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2 | * system.h - SOPC Builder system and BSP software package information
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3 | *
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4 | * Machine generated for CPU 'nios2_gen2_0' in SOPC Builder design 'my_sys'
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5 | * SOPC Builder design path: ../../my_sys.sopcinfo
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6 | *
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7 | * Generated: Wed Jul 31 23:19:21 CEST 2019
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8 | */
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9 |
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10 | /*
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11 | * DO NOT MODIFY THIS FILE
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12 | *
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13 | * Changing this file will have subtle consequences
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14 | * which will almost certainly lead to a nonfunctioning
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15 | * system. If you do modify this file, be aware that your
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16 | * changes will be overwritten and lost when this file
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17 | * is generated again.
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18 | *
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19 | * DO NOT MODIFY THIS FILE
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20 | */
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21 |
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22 | /*
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23 | * License Agreement
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24 | *
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25 | * Copyright (c) 2008
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26 | * Altera Corporation, San Jose, California, USA.
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27 | * All rights reserved.
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28 | *
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29 | * Permission is hereby granted, free of charge, to any person obtaining a
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30 | * copy of this software and associated documentation files (the "Software"),
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31 | * to deal in the Software without restriction, including without limitation
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32 | * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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33 | * and/or sell copies of the Software, and to permit persons to whom the
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34 | * Software is furnished to do so, subject to the following conditions:
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35 | *
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36 | * The above copyright notice and this permission notice shall be included in
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37 | * all copies or substantial portions of the Software.
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38 | *
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39 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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40 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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41 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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42 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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43 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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44 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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45 | * DEALINGS IN THE SOFTWARE.
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46 | *
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47 | * This agreement shall be governed in all respects by the laws of the State
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48 | * of California and by the laws of the United States of America.
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49 | */
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50 |
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51 | #ifndef __SYSTEM_H_
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52 | #define __SYSTEM_H_
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53 |
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54 | /* Include definitions from linker script generator */
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55 | #include "linker.h"
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56 |
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57 |
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58 | /*
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59 | * CPU configuration
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60 | *
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61 | */
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62 |
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63 | #define ALT_CPU_ARCHITECTURE "altera_nios2_gen2"
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64 | #define ALT_CPU_BIG_ENDIAN 0
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65 | #define ALT_CPU_BREAK_ADDR 0x00008820
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66 | #define ALT_CPU_CPU_ARCH_NIOS2_R1
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67 | #define ALT_CPU_CPU_FREQ 50000000u
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68 | #define ALT_CPU_CPU_ID_SIZE 1
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69 | #define ALT_CPU_CPU_ID_VALUE 0x00000000
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70 | #define ALT_CPU_CPU_IMPLEMENTATION "fast"
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71 | #define ALT_CPU_DATA_ADDR_WIDTH 0x10
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72 | #define ALT_CPU_DCACHE_BYPASS_MASK 0x80000000
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73 | #define ALT_CPU_DCACHE_LINE_SIZE 32
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74 | #define ALT_CPU_DCACHE_LINE_SIZE_LOG2 5
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75 | #define ALT_CPU_DCACHE_SIZE 2048
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76 | #define ALT_CPU_EXCEPTION_ADDR 0x00000020
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77 | #define ALT_CPU_FLASH_ACCELERATOR_LINES 0
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78 | #define ALT_CPU_FLASH_ACCELERATOR_LINE_SIZE 0
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79 | #define ALT_CPU_FLUSHDA_SUPPORTED
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80 | #define ALT_CPU_FREQ 50000000
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81 | #define ALT_CPU_HARDWARE_DIVIDE_PRESENT 0
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82 | #define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 1
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83 | #define ALT_CPU_HARDWARE_MULX_PRESENT 0
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84 | #define ALT_CPU_HAS_DEBUG_CORE 1
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85 | #define ALT_CPU_HAS_DEBUG_STUB
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86 | #define ALT_CPU_HAS_EXTRA_EXCEPTION_INFO
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87 | #define ALT_CPU_HAS_ILLEGAL_INSTRUCTION_EXCEPTION
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88 | #define ALT_CPU_HAS_JMPI_INSTRUCTION
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89 | #define ALT_CPU_ICACHE_LINE_SIZE 32
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90 | #define ALT_CPU_ICACHE_LINE_SIZE_LOG2 5
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91 | #define ALT_CPU_ICACHE_SIZE 4096
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92 | #define ALT_CPU_INITDA_SUPPORTED
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93 | #define ALT_CPU_INST_ADDR_WIDTH 0x10
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94 | #define ALT_CPU_NAME "nios2_gen2_0"
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95 | #define ALT_CPU_NUM_OF_SHADOW_REG_SETS 1
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96 | #define ALT_CPU_OCI_VERSION 1
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97 | #define ALT_CPU_RESET_ADDR 0x00000000
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98 |
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99 |
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100 | /*
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101 | * CPU configuration (with legacy prefix - don't use these anymore)
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102 | *
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103 | */
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104 |
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105 | #define NIOS2_BIG_ENDIAN 0
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106 | #define NIOS2_BREAK_ADDR 0x00008820
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107 | #define NIOS2_CPU_ARCH_NIOS2_R1
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108 | #define NIOS2_CPU_FREQ 50000000u
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109 | #define NIOS2_CPU_ID_SIZE 1
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110 | #define NIOS2_CPU_ID_VALUE 0x00000000
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111 | #define NIOS2_CPU_IMPLEMENTATION "fast"
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112 | #define NIOS2_DATA_ADDR_WIDTH 0x10
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113 | #define NIOS2_DCACHE_BYPASS_MASK 0x80000000
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114 | #define NIOS2_DCACHE_LINE_SIZE 32
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115 | #define NIOS2_DCACHE_LINE_SIZE_LOG2 5
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116 | #define NIOS2_DCACHE_SIZE 2048
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117 | #define NIOS2_EXCEPTION_ADDR 0x00000020
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118 | #define NIOS2_FLASH_ACCELERATOR_LINES 0
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119 | #define NIOS2_FLASH_ACCELERATOR_LINE_SIZE 0
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120 | #define NIOS2_FLUSHDA_SUPPORTED
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121 | #define NIOS2_HARDWARE_DIVIDE_PRESENT 0
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122 | #define NIOS2_HARDWARE_MULTIPLY_PRESENT 1
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123 | #define NIOS2_HARDWARE_MULX_PRESENT 0
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124 | #define NIOS2_HAS_DEBUG_CORE 1
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125 | #define NIOS2_HAS_DEBUG_STUB
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126 | #define NIOS2_HAS_EXTRA_EXCEPTION_INFO
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127 | #define NIOS2_HAS_ILLEGAL_INSTRUCTION_EXCEPTION
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128 | #define NIOS2_HAS_JMPI_INSTRUCTION
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129 | #define NIOS2_ICACHE_LINE_SIZE 32
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130 | #define NIOS2_ICACHE_LINE_SIZE_LOG2 5
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131 | #define NIOS2_ICACHE_SIZE 4096
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132 | #define NIOS2_INITDA_SUPPORTED
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133 | #define NIOS2_INST_ADDR_WIDTH 0x10
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134 | #define NIOS2_NUM_OF_SHADOW_REG_SETS 1
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135 | #define NIOS2_OCI_VERSION 1
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136 | #define NIOS2_RESET_ADDR 0x00000000
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137 |
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138 |
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139 | /*
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140 | * Define for each module class mastered by the CPU
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141 | *
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142 | */
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143 |
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144 | #define __ALTERA_AVALON_JTAG_UART
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145 | #define __ALTERA_AVALON_ONCHIP_MEMORY2
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146 | #define __ALTERA_AVALON_PIO
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147 | #define __ALTERA_AVALON_TIMER
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148 | #define __ALTERA_NIOS2_GEN2
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149 |
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150 |
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151 | /*
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152 | * System configuration
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153 | *
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154 | */
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155 |
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156 | #define ALT_DEVICE_FAMILY "Cyclone V"
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157 | #define ALT_ENHANCED_INTERRUPT_API_PRESENT
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158 | #define ALT_IRQ_BASE NULL
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159 | #define ALT_LOG_PORT "/dev/null"
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160 | #define ALT_LOG_PORT_BASE 0x0
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161 | #define ALT_LOG_PORT_DEV null
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162 | #define ALT_LOG_PORT_TYPE ""
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163 | #define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0
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164 | #define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
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165 | #define ALT_NUM_INTERRUPT_CONTROLLERS 1
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166 | #define ALT_STDERR "/dev/jtag_uart_0"
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167 | #define ALT_STDERR_BASE 0x9030
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168 | #define ALT_STDERR_DEV jtag_uart_0
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169 | #define ALT_STDERR_IS_JTAG_UART
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170 | #define ALT_STDERR_PRESENT
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171 | #define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
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172 | #define ALT_STDIN "/dev/jtag_uart_0"
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173 | #define ALT_STDIN_BASE 0x9030
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174 | #define ALT_STDIN_DEV jtag_uart_0
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175 | #define ALT_STDIN_IS_JTAG_UART
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176 | #define ALT_STDIN_PRESENT
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177 | #define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
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178 | #define ALT_STDOUT "/dev/jtag_uart_0"
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179 | #define ALT_STDOUT_BASE 0x9030
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180 | #define ALT_STDOUT_DEV jtag_uart_0
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181 | #define ALT_STDOUT_IS_JTAG_UART
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182 | #define ALT_STDOUT_PRESENT
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183 | #define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
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184 | #define ALT_SYSTEM_NAME "my_sys"
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185 |
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186 |
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187 | /*
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188 | * hal configuration
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189 | *
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190 | */
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191 |
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192 | #define ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
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193 | #define ALT_MAX_FD 4
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194 | #define ALT_SYS_CLK none
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195 | #define ALT_TIMESTAMP_CLK none
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196 |
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197 |
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198 | /*
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199 | * jtag_uart_0 configuration
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200 | *
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201 | */
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202 |
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203 | #define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart
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204 | #define JTAG_UART_0_BASE 0x9030
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205 | #define JTAG_UART_0_IRQ 1
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206 | #define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
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207 | #define JTAG_UART_0_NAME "/dev/jtag_uart_0"
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208 | #define JTAG_UART_0_READ_DEPTH 64
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209 | #define JTAG_UART_0_READ_THRESHOLD 8
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210 | #define JTAG_UART_0_SPAN 8
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211 | #define JTAG_UART_0_TYPE "altera_avalon_jtag_uart"
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212 | #define JTAG_UART_0_WRITE_DEPTH 64
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213 | #define JTAG_UART_0_WRITE_THRESHOLD 8
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214 |
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215 |
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216 | /*
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217 | * onchip_memory2_0 configuration
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218 | *
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219 | */
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220 |
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221 | #define ALT_MODULE_CLASS_onchip_memory2_0 altera_avalon_onchip_memory2
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222 | #define ONCHIP_MEMORY2_0_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
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223 | #define ONCHIP_MEMORY2_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
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224 | #define ONCHIP_MEMORY2_0_BASE 0x0
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225 | #define ONCHIP_MEMORY2_0_CONTENTS_INFO ""
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226 | #define ONCHIP_MEMORY2_0_DUAL_PORT 1
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227 | #define ONCHIP_MEMORY2_0_GUI_RAM_BLOCK_TYPE "AUTO"
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228 | #define ONCHIP_MEMORY2_0_INIT_CONTENTS_FILE "my_sys_onchip_memory2_0"
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229 | #define ONCHIP_MEMORY2_0_INIT_MEM_CONTENT 1
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230 | #define ONCHIP_MEMORY2_0_INSTANCE_ID "NONE"
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231 | #define ONCHIP_MEMORY2_0_IRQ -1
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232 | #define ONCHIP_MEMORY2_0_IRQ_INTERRUPT_CONTROLLER_ID -1
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233 | #define ONCHIP_MEMORY2_0_NAME "/dev/onchip_memory2_0"
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234 | #define ONCHIP_MEMORY2_0_NON_DEFAULT_INIT_FILE_ENABLED 0
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235 | #define ONCHIP_MEMORY2_0_RAM_BLOCK_TYPE "AUTO"
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236 | #define ONCHIP_MEMORY2_0_READ_DURING_WRITE_MODE "DONT_CARE"
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237 | #define ONCHIP_MEMORY2_0_SINGLE_CLOCK_OP 0
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238 | #define ONCHIP_MEMORY2_0_SIZE_MULTIPLE 1
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239 | #define ONCHIP_MEMORY2_0_SIZE_VALUE 30000
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240 | #define ONCHIP_MEMORY2_0_SPAN 30000
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241 | #define ONCHIP_MEMORY2_0_TYPE "altera_avalon_onchip_memory2"
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242 | #define ONCHIP_MEMORY2_0_WRITABLE 1
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243 |
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244 |
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245 | /*
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246 | * pio_0 configuration
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247 | *
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248 | */
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249 |
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250 | #define ALT_MODULE_CLASS_pio_0 altera_avalon_pio
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251 | #define PIO_0_BASE 0x9020
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252 | #define PIO_0_BIT_CLEARING_EDGE_REGISTER 0
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253 | #define PIO_0_BIT_MODIFYING_OUTPUT_REGISTER 0
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254 | #define PIO_0_CAPTURE 0
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255 | #define PIO_0_DATA_WIDTH 8
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256 | #define PIO_0_DO_TEST_BENCH_WIRING 0
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257 | #define PIO_0_DRIVEN_SIM_VALUE 0
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258 | #define PIO_0_EDGE_TYPE "NONE"
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259 | #define PIO_0_FREQ 50000000
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260 | #define PIO_0_HAS_IN 0
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261 | #define PIO_0_HAS_OUT 1
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262 | #define PIO_0_HAS_TRI 0
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263 | #define PIO_0_IRQ -1
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264 | #define PIO_0_IRQ_INTERRUPT_CONTROLLER_ID -1
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265 | #define PIO_0_IRQ_TYPE "NONE"
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266 | #define PIO_0_NAME "/dev/pio_0"
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267 | #define PIO_0_RESET_VALUE 0
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268 | #define PIO_0_SPAN 16
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269 | #define PIO_0_TYPE "altera_avalon_pio"
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270 |
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271 |
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272 | /*
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273 | * timer_0 configuration
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274 | *
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275 | */
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276 |
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277 | #define ALT_MODULE_CLASS_timer_0 altera_avalon_timer
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278 | #define TIMER_0_ALWAYS_RUN 0
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279 | #define TIMER_0_BASE 0x9000
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280 | #define TIMER_0_COUNTER_SIZE 32
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281 | #define TIMER_0_FIXED_PERIOD 0
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282 | #define TIMER_0_FREQ 50000000
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283 | #define TIMER_0_IRQ 0
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284 | #define TIMER_0_IRQ_INTERRUPT_CONTROLLER_ID 0
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285 | #define TIMER_0_LOAD_VALUE 49999
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286 | #define TIMER_0_MULT 0.001
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287 | #define TIMER_0_NAME "/dev/timer_0"
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288 | #define TIMER_0_PERIOD 1
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289 | #define TIMER_0_PERIOD_UNITS "ms"
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290 | #define TIMER_0_RESET_OUTPUT 0
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291 | #define TIMER_0_SNAPSHOT 1
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292 | #define TIMER_0_SPAN 32
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293 | #define TIMER_0_TICKS_PER_SEC 1000
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294 | #define TIMER_0_TIMEOUT_PULSE_OUTPUT 0
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295 | #define TIMER_0_TYPE "altera_avalon_timer"
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296 |
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297 | #endif /* __SYSTEM_H_ */
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