Hallo,
bin nun gerade dabei mich in das EDK 10.1 einzuarbeiten.
Ich würde nun gern mit dem selben xps_gpio Interface (welches eine
Breite von 2 Bit hat) sowohl einen Ausgang (also eine LED), als auch
einen Eingang (Schalter auf dem Spartan3E Starter Kit Board) ansteuern.
Mein UCS-File:
1 | ############################################################################
|
2 | ## This system.ucf file is generated by Base System Builder based on the
|
3 | ## settings in the selected Xilinx Board Definition file. Please add other
|
4 | ## user constraints to this file based on customer design specifications.
|
5 | ############################################################################
|
6 |
|
7 | Net sys_clk_pin LOC=c9;
|
8 | Net sys_clk_pin IOSTANDARD = LVCMOS33;
|
9 | Net sys_rst_pin LOC=K17;
|
10 | Net sys_rst_pin IOSTANDARD = LVCMOS33;
|
11 | Net sys_rst_pin PULLDOWN;
|
12 | ## System level constraints
|
13 | Net sys_clk_pin TNM_NET = sys_clk_pin;
|
14 | TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 20000 ps;
|
15 | Net sys_rst_pin TIG;
|
16 |
|
17 | ## IO Devices constraints
|
18 |
|
19 | #### Module RS232_DCE constraints
|
20 |
|
21 | Net fpga_0_RS232_DCE_RX_pin LOC=R7;
|
22 | Net fpga_0_RS232_DCE_RX_pin IOSTANDARD = LVCMOS33;
|
23 | Net fpga_0_RS232_DCE_TX_pin LOC=M14;
|
24 | Net fpga_0_RS232_DCE_TX_pin IOSTANDARD = LVCMOS33;
|
25 |
|
26 | Net xps_gpio_0_GPIO_IO<0> LOC=F12;
|
27 | Net xps_gpio_0_GPIO_IO<0> IOSTANDARD = LVCMOS33;
|
28 | Net xps_gpio_0_GPIO_IO<1> LOC=H18;
|
29 | Net xps_gpio_0_GPIO_IO<1> IOSTANDARD = LVCMOS33;
|
30 | Net xps_gpio_0_GPIO_IO<1> PULLDOWN;
|
31 |
|
32 | # wenn ich für den Eingang ein eigenes GPIO-Interface nehme - dann geht es...???
|
33 | Net xps_gpio_1_GPIO_IO_I_pin<0> LOC=N17;
|
34 | Net xps_gpio_1_GPIO_IO_I_pin<0> IOSTANDARD = LVCMOS33;
|
35 | Net xps_gpio_1_GPIO_IO_I_pin<0> PULLDOWN;
|
Die Fehlermeldung von map:
1 | #----------------------------------------------#
|
2 | # Starting program map
|
3 | # map -o system_map.ncd -pr b -ol high -timing system.ngd system.pcf
|
4 | #----------------------------------------------#
|
5 | Release 10.1.03 - Map K.39 (nt)
|
6 | Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
|
7 | PMSPEC -- Overriding Xilinx file <C:/Xilinx/10.1/EDK/data/Xdh_PrimTypeLib.xda>
|
8 | with local file <c:/Xilinx/10.1/ISE/data/Xdh_PrimTypeLib.xda>
|
9 | Using target part "3s500efg320-4".
|
10 | Writing file system_map.ngm...
|
11 | Running directed packing...
|
12 | ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB
|
13 | component:
|
14 | PAD symbol "xps_gpio_0_GPIO_IO<1>" (Pad Signal = xps_gpio_0_GPIO_IO<1>)
|
15 | PULL symbol "xps_gpio_0_GPIO_IO<1>_PULLDOWN" (Output Signal =
|
16 | xps_gpio_0_GPIO_IO<1>)
|
17 | TBUF symbol "iobuf_1/OBUFT" (Control Signal = xps_gpio_0_GPIO_IO_T<1>)
|
18 | BUF symbol "iobuf_1/IBUF" (Output Signal = xps_gpio_0_GPIO_IO_I<1>)
|
19 | An IO component of type IOB was chosen because the IO contains symbols and/or
|
20 | properties consistent with output or bi-directional usage and contains no
|
21 | other symbols or properties that require a more specific IO component type.
|
22 | Each of the following constraints specifies an illegal physical site for a
|
23 | component of type IOB:
|
24 | Symbol "xps_gpio_0_GPIO_IO<1>" (LOC=H18 [Physical Site Type = IBUF])
|
25 | The component type is determined by the types of logic and the properties and
|
26 | configuration of the logic it contains. Please double check that the types of
|
27 | logic elements and all of their relevant properties and configuration options
|
28 | are compatible with the physical site type of the constraint.
|
29 | Please correct the constraints accordingly.
|
30 |
|
31 | Mapping completed.
|
32 | See MAP report file "system_map.mrp" for details.
|
33 | Problem encountered during the packing phase.
|
34 |
|
35 | Design Summary
|
36 | --------------
|
37 | Number of errors : 1
|
38 | Number of warnings : 2
|
39 | ERROR:Xflow - Program map returned error code 2. Aborting flow execution...
|
40 | Done!
|
Kann mir jemand helfen? Oder ist es tatsächlich so, dass man für so eine
anwendung ZWEI GPIO-Interfaces braucht?
Mir ist klar, dass ich später so eine Aufgabe sicherlich einer eigenen
IP geben werde. Ich würde mich nur gern jetzt in die Funktionalität der
GPIO-IP einarbeiten und diese vollständig verstehen...
Beste Grüße,
Andreas