Hallo, wir haben vor aus einer Sägezahn Spannung eine Sinus Spannung zu generieren.
1 | library IEEE; |
2 | use IEEE.STD_LOGIC_1164.ALL; |
3 | use IEEE.STD_LOGIC_ARITH.ALL; |
4 | use IEEE.MATH_REAL.ALL; |
5 | |
6 | entity SinusGeneration is |
7 | Port
|
8 | (
|
9 | clkin : in std_logic; |
10 | reset_n : in std_logic; |
11 | cnt_in : in std_logic_vector(13 downto 0); |
12 | cnt_out : out std_logic_vector(13 downto 0) |
13 | );
|
14 | end SinusGeneration; |
15 | |
16 | architecture Behavioral of SinusGeneration is |
17 | signal state: std_logic_vector(1 downto 0); |
18 | begin
|
19 | --signal dac: std_logic_vector(13 downto 0);
|
20 | sin_gen: process(cnt_in) |
21 | variable value1: integer range 0 to 16383; |
22 | --variable state: integer;
|
23 | begin
|
24 | if reset_n = '0' then |
25 | state <= "00"; |
26 | elsif (clkin = '1') and (clkin'event) then |
27 | value1 := conv_integer(unsigned(cnt_in)); |
28 | if (state = "00") then |
29 | cnt_out <= conv_std_logic_vector((8191 + value1), 14); |
30 | if (value1 = 8192) then |
31 | state <= "01"; |
32 | end if; |
33 | end if; |
34 | if (state = "01") then |
35 | cnt_out <= conv_std_logic_vector(8191 + (16383 - value1), 14); |
36 | if ((16383 - value1) = 0) then |
37 | state <= "10"; |
38 | end if; |
39 | end if; |
40 | if (state = "10") then |
41 | cnt_out <= conv_std_logic_vector((8191 - value1), 14); |
42 | if (value1 = 8192) then |
43 | state <= "11"; |
44 | end if; |
45 | end if; |
46 | if (state = "11") then |
47 | cnt_out <= conv_std_logic_vector(8191 - (16383 - value1), 14); |
48 | if ((16383 - value1) = 0) then |
49 | state <= "00"; |
50 | end if; |
51 | end if; |
52 | |
53 | end if; |
54 | end process sin_gen; |
55 | end Behavioral; |
Jemand eine Idee? Evtl mit Hilfe eines Filters? Oder der Sinus Funktion in vhdl? MfG Jens&Max