Hi, als kleines Vorwort:"Ich bin noch recht unerfahren mit VHDL" Ich habe Desing mit mehreren Komponenten und bin gerade an dem Punkt die Komponenten untereinander zuverknüpfen. Allerdings scheint es so das ich dabei Fehler mache. Ich benutze zum entwickeln ispLever + Aldec Active HDL Unzwar habe ich in meiner top-entity einen in-port "Clk_G". Welchen ich in der im testbench-file auch stimuliere. Dies wird mir auch in der Simulation angezeigt. Nun möchte ich diesen Port(Clk_G) auf die Clk-Ports der einzelnen Komponenten mappen. Allerdings werden mir die Clk-ports der Komponenten als "undefined" angezeigt und bleiben es auch und das obwohl der "Clk_G" unermütlich zwischen "1" und "0" wechselt. Hier meine top.vhdl:
1 | library ieee; |
2 | use ieee.std_logic_1164.all; |
3 | use ieee.std_logic_arith.all; |
4 | use ieee.std_logic_unsigned.all; |
5 | |
6 | entity top is |
7 | generic (ii : natural := 0); |
8 | |
9 | port( |
10 | Clk_G : in std_logic; |
11 | S_Reset : in std_logic; |
12 | -- out-ports from the environment
|
13 | H : out std_logic; |
14 | V : out std_logic; |
15 | DE_out : out std_logic; |
16 | Re : out std_logic_vector (7 downto 0); |
17 | Gr : out std_logic_vector (7 downto 0); |
18 | Bl : out std_logic_vector (7 downto 0); |
19 | Pixels_Tot : inout std_logic_vector (11 downto 0); |
20 | Lines_Tot : inout std_logic_vector (10 downto 0); |
21 | Pixels_Act : out std_logic_vector (11 downto 0); |
22 | Lines_Act : out std_logic_vector (10 downto 0); |
23 | Hor_sync : out std_logic_vector (5 downto 0); |
24 | Ver_sync : out std_logic_vector (5 downto 0); |
25 | Hor_F_P : out std_logic_vector (9 downto 0); |
26 | Hor_B_P : out std_logic_vector (9 downto 0); |
27 | H_sync_Pol : out std_logic; |
28 | Ver_F_P : out std_logic_vector (2 downto 0); |
29 | Ver_B_P : out std_logic_vector (5 downto 0); |
30 | V_sync_Pol : out std_logic |
31 | |
32 | );
|
33 | |
34 | end; |
35 | |
36 | architecture top_arch of top is |
37 | -- buffer-signals to hand the analysis-result(aResult_) data to the mux_displayUnit(anaResult_)
|
38 | signal tempAnaResult_pixHorizontal : std_logic_vector(11 downto 0); |
39 | signal tempAnaResult_linesVertical : std_logic_vector(10 downto 0); |
40 | signal tempAnaResult_pixTotalHorizontal : std_logic_vector(11 downto 0); |
41 | signal tempAnaResult_linesTotalVertical : std_logic_vector(10 downto 0); |
42 | signal tempAnaResult_syncPixHorizontal : std_logic_vector(5 downto 0); |
43 | signal tempAnaResult_syncPixVertical : std_logic_vector(5 downto 0); |
44 | signal tempAnaResult_frontPorchHorizontal : std_logic_vector(9 downto 0); |
45 | signal tempAnaResult_frontPorchVertical : std_logic_vector(2 downto 0); |
46 | signal tempAnaResult_backPorchHorizontal : std_logic_vector(9 downto 0); |
47 | signal tempAnaResult_backPorchVertical : std_logic_vector(5 downto 0); |
48 | signal tempAnaResult_syncPolarityHorizontal : std_logic; |
49 | signal tempAnaResult_syncPolarityVertical : std_logic; |
50 | signal sel : std_logic_vector(7 downto 0); |
51 | signal du_horizontalPix : natural; -- active horizontal pix |
52 | signal du_verticalLines : natural; -- active vertical lines |
53 | signal du_horizontalTotalPix : natural; -- total horizontal pix (active pix + frontporch + etc.) |
54 | signal du_verticalTotalLines : natural; -- total vertical lines (active lines + frontporch + etc.) |
55 | signal du_horizontalSyncPix : natural; -- horizontal pix-size for the sync-signal |
56 | signal du_verticalSyncPix : natural; -- vertical line-size for the sync-signal |
57 | signal du_horizontalFrontPorch : natural; -- horizontal frontporch |
58 | signal du_horizontalBackPorch : natural; -- horizontal backporch |
59 | signal du_verticalFrontPorch : natural; -- vertical frontporch |
60 | signal du_verticalBackPorch : natural; -- vertical backporch |
61 | signal du_hSyncPolarity : std_logic; -- HSync-Polarity |
62 | signal du_vSyncPolarity : std_logic; -- VSync-Polarity |
63 | signal manual_pixHorizontal : natural; |
64 | signal manual_linesVertical : natural; |
65 | signal manual_pixTotalHorizontal : natural; |
66 | signal manual_linesTotalVertical : natural; |
67 | signal manual_syncPixHorizontal : natural; |
68 | signal manual_syncPixVertical : natural; |
69 | signal manual_frontPorchHorizontal : natural; |
70 | signal manual_frontPorchVertical : natural; |
71 | signal manual_backPorchHorizontal : natural; |
72 | signal manual_backPorchVertical : natural; |
73 | signal manual_syncPolarityHorizontal : std_logic; |
74 | signal manual_syncPolarityVertical : std_logic; |
75 | signal resetFormatChange : std_logic; |
76 | |
77 | signal clock : std_logic; |
78 | |
79 | |
80 | component displayunit |
81 | generic (i : natural := 0); |
82 | port( |
83 | clk : in std_logic; |
84 | reset : in std_logic; |
85 | DE : out std_logic; |
86 | hSync : out std_logic; |
87 | vSync : out std_logic; |
88 | R : out std_logic_vector (7 downto 0); |
89 | G : out std_logic_vector (7 downto 0); |
90 | B : out std_logic_vector (7 downto 0); |
91 | -- in-ports from the displayUnit
|
92 | du_horizontalPix : in natural; -- active horizontal pix |
93 | du_verticalLines : in natural; -- active vertical lines |
94 | du_horizontalTotalPix : in natural; -- total horizontal pix (active pix + frontporch + etc.) |
95 | du_verticalTotalLines : in natural; -- total vertical lines (active lines + frontporch + etc.) |
96 | du_horizontalSyncPix : in natural; -- horizontal pix-size for the sync-signal |
97 | du_verticalSyncPix : in natural; -- vertical line-size for the sync-signal |
98 | du_horizontalFrontPorch : in natural; -- horizontal frontporch |
99 | du_horizontalBackPorch : in natural; -- horizontal backporch |
100 | du_verticalFrontPorch : in natural; -- vertical frontporch |
101 | du_verticalBackPorch : in natural; -- vertical backporch |
102 | du_hSyncPolarity : in std_logic; -- HSync-Polarity |
103 | du_vSyncPolarity : in std_logic -- VSync-Polarity |
104 | );
|
105 | |
106 | |
107 | end component; |
108 | signal internH, internV, internDE : std_logic; |
109 | |
110 | component analysis |
111 | port( |
112 | -- in-ports for the analysis(handed by the video-in-port)
|
113 | analysisClk : in std_logic; |
114 | analysisReset : in std_logic; |
115 | analysisHSync : in std_logic; |
116 | analysisVSync : in std_logic; |
117 | analysisDE : in std_logic; |
118 | -- out-port from analysis(signal to alert about a format-change)
|
119 | formatChange : out std_logic; |
120 | -- in-port from analysis(to reset the formatChange-signal)
|
121 | resetFormatChange : in std_logic; |
122 | -- out-ports from the analysis
|
123 | aResult_totalPix : inout std_logic_vector (11 downto 0); |
124 | aResult_totalLines : inout std_logic_vector (10 downto 0); |
125 | aResult_activePix : out std_logic_vector (11 downto 0); |
126 | aResult_activeLines : out std_logic_vector (10 downto 0); |
127 | aResult_hSync : out std_logic_vector (5 downto 0); |
128 | aResult_vSync : out std_logic_vector (5 downto 0); |
129 | aResult_horizontalFrontPorch : out std_logic_vector (9 downto 0); |
130 | aResult_horizontalBackPorch : out std_logic_vector (9 downto 0); |
131 | aResult_hSyncPolarity : out std_logic; |
132 | aResult_verticalFrontPorch : out std_logic_vector (2 downto 0); |
133 | aResult_verticalBackPorch : out std_logic_vector (5 downto 0); |
134 | aResult_vSyncPolarity : out std_logic |
135 | );
|
136 | end component; |
137 | |
138 | component mux_displayUnit |
139 | port( |
140 | muxClk : in std_logic; |
141 | -- in-port from mux_displayUnit(to select the source of format-data)
|
142 | sel : in std_logic_vector (7 downto 0); |
143 | -- in-port from analysis(to reset the formatChange-signal)
|
144 | anaResult_pixHorizontal : in std_logic_vector(11 downto 0); |
145 | anaResult_linesVertical : in std_logic_vector(10 downto 0); |
146 | anaResult_pixTotalHorizontal : in std_logic_vector(11 downto 0); |
147 | anaResult_linesTotalVertical : in std_logic_vector(10 downto 0); |
148 | anaResult_syncPixHorizontal : in std_logic_vector(5 downto 0); |
149 | anaResult_syncPixVertical : in std_logic_vector(5 downto 0); |
150 | anaResult_frontPorchHorizontal : in std_logic_vector(9 downto 0); |
151 | anaResult_frontPorchVertical : in std_logic_vector(2 downto 0); |
152 | anaResult_backPorchHorizontal : in std_logic_vector(9 downto 0); |
153 | anaResult_backPorchVertical : in std_logic_vector(5 downto 0); |
154 | anaResult_syncPolarityHorizontal : in std_logic; |
155 | anaResult_syncPolarityVertical : in std_logic; |
156 | -- in-ports from mux_displayUnit(manual-input handed by the localbus)
|
157 | manual_pixHorizontal : in natural; |
158 | manual_linesVertical : in natural; |
159 | manual_pixTotalHorizontal : in natural; |
160 | manual_linesTotalVertical : in natural; |
161 | manual_syncPixHorizontal : in natural; |
162 | manual_syncPixVertical : in natural; |
163 | manual_frontPorchHorizontal : in natural; |
164 | manual_frontPorchVertical : in natural; |
165 | manual_backPorchHorizontal : in natural; |
166 | manual_backPorchVertical : in natural; |
167 | manual_syncPolarityHorizontal : in std_logic; |
168 | manual_syncPolarityVertical : in std_logic; |
169 | -- resultdata which will be handed to the displayUnit
|
170 | result_pixHorizontal : out std_logic_vector(11 downto 0); |
171 | result_linesVertical : out std_logic_vector(10 downto 0); |
172 | result_pixTotalHorizontal : out std_logic_vector(11 downto 0); |
173 | result_linesTotalVertical : out std_logic_vector(10 downto 0); |
174 | result_syncPixHorizontal : out std_logic_vector(5 downto 0); |
175 | result_syncPixVertical : out std_logic_vector(5 downto 0); |
176 | result_frontPorchHorizontal : out std_logic_vector(9 downto 0); |
177 | result_frontPorchVertical : out std_logic_vector(2 downto 0); |
178 | result_backPorchHorizontal : out std_logic_vector(9 downto 0); |
179 | result_backPorchVertical : out std_logic_vector(5 downto 0); |
180 | result_syncPolarityHorizontal : out std_logic; |
181 | result_syncPolarityVertical : out std_logic |
182 | );
|
183 | end component; |
184 | |
185 | |
186 | begin
|
187 | |
188 | |
189 | clock <= Clk_G ; |
190 | |
191 | |
192 | aa: displayunit |
193 | port map( |
194 | clk => Clk_G, |
195 | reset => S_Reset, |
196 | DE => internDE, |
197 | hSync => internH, |
198 | vSync => internV, |
199 | R => Re, |
200 | G => Gr, |
201 | B => Bl, |
202 | du_horizontalPix => du_horizontalPix, |
203 | du_verticalLines => du_verticalLines, |
204 | du_horizontalTotalPix => du_horizontalTotalPix, |
205 | du_verticalTotalLines => du_verticalTotalLines, |
206 | du_horizontalSyncPix => du_horizontalSyncPix, |
207 | du_verticalSyncPix => du_verticalSyncPix, |
208 | du_horizontalFrontPorch => du_horizontalFrontPorch, |
209 | du_horizontalBackPorch => du_horizontalBackPorch, |
210 | du_verticalFrontPorch => du_verticalFrontPorch, |
211 | du_verticalBackPorch => du_verticalBackPorch, |
212 | du_hSyncPolarity => du_hSyncPolarity, |
213 | du_vSyncPolarity => du_vSyncPolarity |
214 | );
|
215 | |
216 | bb: analysis |
217 | port map( |
218 | --
|
219 | analysisClk => Clk_G, |
220 | analysisReset => S_Reset, |
221 | analysisHSync => internH, |
222 | analysisVSync => internV, |
223 | analysisDE => internDE, |
224 | -- out-ports(results) of analysis mapped on the buffer-signals
|
225 | aResult_totalPix => tempAnaResult_pixTotalHorizontal, |
226 | aResult_totalLines => tempAnaResult_linesTotalVertical, |
227 | aResult_activePix => tempAnaResult_pixHorizontal, |
228 | aResult_activeLines => tempAnaResult_linesVertical, |
229 | aResult_hSync => tempAnaResult_syncPixHorizontal, |
230 | aResult_vSync => tempAnaResult_syncPixVertical, |
231 | aResult_horizontalFrontPorch => tempAnaResult_frontPorchHorizontal, |
232 | aResult_horizontalBackPorch => tempAnaResult_backPorchHorizontal, |
233 | aResult_hSyncPolarity => tempAnaResult_syncPolarityHorizontal, |
234 | aResult_verticalFrontPorch => tempAnaResult_frontPorchVertical, |
235 | aResult_verticalBackPorch => tempAnaResult_backPorchVertical, |
236 | aResult_vSyncPolarity => tempAnaResult_syncPolarityVertical, |
237 | -- formatChange => formatChange,
|
238 | resetFormatChange => resetFormatChange |
239 | );
|
240 | |
241 | cc: mux_displayUnit |
242 | port map( |
243 | muxClk => clock, |
244 | -- in-ports from mux_displayUnit mapped on the buffer-signals
|
245 | anaResult_pixTotalHorizontal => tempAnaResult_pixTotalHorizontal, |
246 | anaResult_linesTotalVertical => tempAnaResult_linesTotalVertical, |
247 | anaResult_pixHorizontal => tempAnaResult_pixHorizontal, |
248 | anaResult_linesVertical => tempAnaResult_linesVertical, |
249 | anaResult_syncPixHorizontal => tempAnaResult_syncPixHorizontal, |
250 | anaResult_syncPixVertical => tempAnaResult_syncPixVertical, |
251 | anaResult_frontPorchHorizontal => tempAnaResult_frontPorchHorizontal, |
252 | anaResult_backPorchHorizontal => tempAnaResult_backPorchHorizontal, |
253 | anaResult_syncPolarityHorizontal => tempAnaResult_syncPolarityHorizontal, |
254 | anaResult_frontPorchVertical => tempAnaResult_frontPorchVertical, |
255 | anaResult_backPorchVertical => tempAnaResult_backPorchVertical, |
256 | anaResult_syncPolarityVertical => tempAnaResult_syncPolarityVertical, |
257 | manual_pixHorizontal => manual_pixHorizontal, |
258 | manual_linesVertical => manual_linesVertical, |
259 | manual_pixTotalHorizontal => manual_pixTotalHorizontal, |
260 | manual_linesTotalVertical => manual_linesTotalVertical, |
261 | manual_syncPixHorizontal => manual_syncPixHorizontal, |
262 | manual_syncPixVertical => manual_syncPixVertical, |
263 | manual_frontPorchHorizontal => manual_frontPorchHorizontal, |
264 | manual_frontPorchVertical => manual_frontPorchVertical, |
265 | manual_backPorchHorizontal => manual_backPorchHorizontal, |
266 | manual_backPorchVertical => manual_backPorchVertical, |
267 | manual_syncPolarityHorizontal => manual_syncPolarityHorizontal, |
268 | manual_syncPolarityVertical => manual_syncPolarityVertical, |
269 | sel => sel |
270 | );
|
271 | H <= internH; |
272 | V <= internV; |
273 | DE_out <= internDE; |
274 | |
275 | end top_arch; |
wie man sehen kann hab ich versucht den "muxClk" über ein zwischensignal("clock") zu mappen. Aber auch das fürht zu keinerlei aktivität des "muxClk" in der Simulation. Ein weiteres Indiz dafür das mit dem mapping was nicht stimmt ist das wenn ich im Active-HDL(Simulation) auf das "muxClk"-signal den Befehl "View in Dataflow" ausführe mir keinerlei Verknüpfungen Angezeigt werden. Eventuell aber ist ja auch mein Fehler in der testbench selbst zufinden vondaher hier:
1 | library ieee; |
2 | use ieee.std_logic_1164.all; |
3 | use ieee.numeric_std.all; |
4 | use work.formats.all; |
5 | |
6 | entity testbench is |
7 | end testbench; |
8 | |
9 | architecture behavior of testbench is |
10 | |
11 | component top |
12 | generic (ii : natural :=0); |
13 | --generic (iii : natural :=0);
|
14 | port( |
15 | Clk_G : in std_logic; |
16 | S_Reset : in std_logic; |
17 | resetFormatChange : in std_logic; |
18 | formatChange : out std_logic; |
19 | |
20 | anaResult_pixHorizontal : in std_logic_vector(11 downto 0); |
21 | anaResult_linesVertical : in std_logic_vector(10 downto 0); |
22 | anaResult_pixTotalHorizontal : in std_logic_vector(11 downto 0); |
23 | anaResult_linesTotalVertical : in std_logic_vector(10 downto 0); |
24 | anaResult_syncPixHorizontal : in std_logic_vector(5 downto 0); |
25 | anaResult_syncPixVertical : in std_logic_vector(5 downto 0); |
26 | anaResult_frontPorchHorizontal : in std_logic_vector(9 downto 0); |
27 | anaResult_frontPorchVertical : in std_logic_vector(2 downto 0); |
28 | anaResult_backPorchHorizontal : in std_logic_vector(9 downto 0); |
29 | anaResult_backPorchVertical : in std_logic_vector(5 downto 0); |
30 | anaResult_syncPolarityHorizontal : in std_logic; |
31 | anaResult_syncPolarityVertical : in std_logic; |
32 | |
33 | analysisClk : in std_logic; |
34 | analysisReset : in std_logic; |
35 | analysisHSync : in std_logic; |
36 | analysisVSync : in std_logic; |
37 | analysisDE : in std_logic; |
38 | |
39 | aResult_totalPix : inout std_logic_vector (11 downto 0); |
40 | aResult_totalLines : inout std_logic_vector (10 downto 0); |
41 | aResult_activePix : out std_logic_vector (11 downto 0); |
42 | aResult_activeLines : out std_logic_vector (10 downto 0); |
43 | aResult_hSync : out std_logic_vector (5 downto 0); |
44 | aResult_vSync : out std_logic_vector (5 downto 0); |
45 | aResult_horizontalFrontPorch : out std_logic_vector (9 downto 0); |
46 | aResult_horizontalBackPorch : out std_logic_vector (9 downto 0); |
47 | aResult_hSyncPolarity : out std_logic; |
48 | aResult_verticalFrontPorch : out std_logic_vector (2 downto 0); |
49 | aResult_verticalBackPorch : out std_logic_vector (5 downto 0); |
50 | aResult_vSyncPolarity : out std_logic; |
51 | |
52 | muxClk : in std_logic; |
53 | |
54 | sel : in std_logic_vector (7 downto 0); |
55 | |
56 | result_pixHorizontal : out std_logic_vector(11 downto 0); |
57 | result_linesVertical : out std_logic_vector(10 downto 0); |
58 | result_pixTotalHorizontal : out std_logic_vector(11 downto 0); |
59 | result_linesTotalVertical : out std_logic_vector(10 downto 0); |
60 | result_syncPixHorizontal : out std_logic_vector(5 downto 0); |
61 | result_syncPixVertical : out std_logic_vector(5 downto 0); |
62 | result_frontPorchHorizontal : out std_logic_vector(9 downto 0); |
63 | result_frontPorchVertical : out std_logic_vector(2 downto 0); |
64 | result_backPorchHorizontal : out std_logic_vector(9 downto 0); |
65 | result_backPorchVertical : out std_logic_vector(5 downto 0); |
66 | result_syncPolarityHorizontal : out std_logic; |
67 | result_syncPolarityVertical : out std_logic; |
68 | |
69 | H : out std_logic; |
70 | V : out std_logic; |
71 | DE_out : out std_logic; |
72 | Pixels_Act : out std_logic_vector (11 downto 0); |
73 | Lines_Act : out std_logic_vector (10 downto 0); |
74 | Hor_sync : out std_logic_vector (5 downto 0); |
75 | Ver_sync : out std_logic_vector (5 downto 0); |
76 | Re : out std_logic_vector (7 downto 0); |
77 | Gr : out std_logic_vector (7 downto 0); |
78 | Bl : out std_logic_vector (7 downto 0); |
79 | Hor_F_P : out std_logic_vector (9 downto 0); |
80 | Hor_B_P : out std_logic_vector (9 downto 0); |
81 | H_sync_Pol : out std_logic; |
82 | Ver_F_P : out std_logic_vector (2 downto 0); |
83 | Ver_B_P : out std_logic_vector (5 downto 0); |
84 | V_sync_Pol : out std_logic; |
85 | Pixels_Tot : inout std_logic_vector (11 downto 0); |
86 | Lines_Tot : inout std_logic_vector (10 downto 0) |
87 | );
|
88 | end component; |
89 | |
90 | signal Clk_G : std_logic; |
91 | signal S_Reset : std_logic; |
92 | signal H : std_logic; |
93 | signal V : std_logic; |
94 | signal DE_out : std_logic; |
95 | signal Pixels_Tot : std_logic_vector (11 downto 0); |
96 | signal Lines_Tot : std_logic_vector (10 downto 0); |
97 | signal Pixels_Act : std_logic_vector (11 downto 0); |
98 | signal Lines_Act : std_logic_vector (10 downto 0); |
99 | signal Hor_sync : std_logic_vector (5 downto 0); |
100 | signal Ver_sync : std_logic_vector (5 downto 0); |
101 | signal Re : std_logic_vector (7 downto 0); |
102 | signal Gr : std_logic_vector (7 downto 0); |
103 | signal Bl : std_logic_vector (7 downto 0); |
104 | signal Hor_F_P : std_logic_vector (9 downto 0); |
105 | signal Hor_B_P : std_logic_vector (9 downto 0); |
106 | signal H_sync_Pol : std_logic; |
107 | signal Ver_F_P : std_logic_vector (2 downto 0); |
108 | signal Ver_B_P : std_logic_vector (5 downto 0); |
109 | signal V_sync_Pol : std_logic; |
110 | signal resetFormatChange : std_logic; |
111 | signal formatChange : std_logic; |
112 | signal iii : natural; |
113 | signal du_horizontalPix : natural; -- active horizontal pix |
114 | signal du_verticalLines : natural; -- active vertical lines |
115 | signal du_horizontalTotalPix : natural; -- total horizontal pix (active pix + frontporch + etc.) |
116 | signal du_verticalTotalLines : natural; -- total vertical lines (active lines + frontporch + etc.) |
117 | signal du_horizontalSyncPix : natural; -- horizontal pix-size for the sync-signal |
118 | signal du_verticalSyncPix : natural; -- vertical line-size for the sync-signal |
119 | signal du_horizontalFrontPorch : natural; -- horizontal frontporch |
120 | signal du_horizontalBackPorch : natural; -- horizontal backporch |
121 | signal du_verticalFrontPorch : natural; -- vertical frontporch |
122 | signal du_verticalBackPorch : natural; -- vertical backporch |
123 | signal du_hSyncPolarity : std_logic; -- HSync-Polarity |
124 | signal du_vSyncPolarity : std_logic; -- VSync-Polarity |
125 | |
126 | signal analysisHSync : std_logic; |
127 | signal analysisVSync : std_logic; |
128 | signal analysisDE : std_logic; |
129 | signal analysisClk : std_logic; |
130 | signal analysisReset : std_logic; |
131 | |
132 | signal anaResult_pixHorizontal : std_logic_vector(11 downto 0); |
133 | signal anaResult_linesVertical : std_logic_vector(10 downto 0); |
134 | signal anaResult_pixTotalHorizontal : std_logic_vector(11 downto 0); |
135 | signal anaResult_linesTotalVertical : std_logic_vector(10 downto 0); |
136 | signal anaResult_syncPixHorizontal : std_logic_vector(5 downto 0); |
137 | signal anaResult_syncPixVertical : std_logic_vector(5 downto 0); |
138 | signal anaResult_frontPorchHorizontal : std_logic_vector(9 downto 0); |
139 | signal anaResult_frontPorchVertical : std_logic_vector(2 downto 0); |
140 | signal anaResult_backPorchHorizontal : std_logic_vector(9 downto 0); |
141 | signal anaResult_backPorchVertical : std_logic_vector(5 downto 0); |
142 | signal anaResult_syncPolarityHorizontal : std_logic; |
143 | signal anaResult_syncPolarityVertical : std_logic; |
144 | |
145 | signal sel : std_logic_vector (7 downto 0); |
146 | |
147 | signal result_pixHorizontal : std_logic_vector(11 downto 0); |
148 | signal result_linesVertical : std_logic_vector(10 downto 0); |
149 | signal result_pixTotalHorizontal : std_logic_vector(11 downto 0); |
150 | signal result_linesTotalVertical : std_logic_vector(10 downto 0); |
151 | signal result_syncPixHorizontal : std_logic_vector(5 downto 0); |
152 | signal result_syncPixVertical : std_logic_vector(5 downto 0); |
153 | signal result_frontPorchHorizontal : std_logic_vector(9 downto 0); |
154 | signal result_frontPorchVertical : std_logic_vector(2 downto 0); |
155 | signal result_backPorchHorizontal : std_logic_vector(9 downto 0); |
156 | signal result_backPorchVertical : std_logic_vector(5 downto 0); |
157 | signal result_syncPolarityHorizontal : std_logic; |
158 | signal result_syncPolarityVertical : std_logic; |
159 | signal muxClk : std_logic; |
160 | |
161 | |
162 | |
163 | begin
|
164 | |
165 | -- Please check and add your generic clause manually
|
166 | uut: top |
167 | generic map (ii => iii) |
168 | port map( |
169 | Clk_G => Clk_G, |
170 | S_Reset => S_Reset, |
171 | H => H, |
172 | V => V, |
173 | DE_out => DE_out, |
174 | Pixels_Tot => Pixels_Tot, |
175 | Lines_Tot => Lines_Tot, |
176 | Pixels_Act => Pixels_Act, |
177 | Lines_Act => Lines_Act, |
178 | Hor_sync => Hor_sync, |
179 | Ver_sync => Ver_sync, |
180 | Re => Re, |
181 | Gr => Gr, |
182 | Bl => Bl, |
183 | Hor_F_P => Hor_F_P, |
184 | Hor_B_P => Hor_B_P, |
185 | H_sync_Pol => H_sync_Pol, |
186 | Ver_F_P => Ver_F_P, |
187 | Ver_B_P => Ver_B_P, |
188 | V_sync_Pol => V_sync_Pol, |
189 | resetFormatChange => resetFormatChange, |
190 | formatChange => formatChange, |
191 | analysisClk => analysisClk, |
192 | analysisReset => analysisReset, |
193 | analysisHSync => analysisHSync, |
194 | analysisVSync => analysisVSync, |
195 | analysisDE => analysisDE, |
196 | anaResult_pixHorizontal =>anaResult_pixHorizontal, |
197 | anaResult_linesVertical =>anaResult_linesVertical, |
198 | anaResult_pixTotalHorizontal =>anaResult_pixTotalHorizontal, |
199 | anaResult_linesTotalVertical =>anaResult_linesTotalVertical, |
200 | anaResult_syncPixHorizontal =>anaResult_syncPixHorizontal, |
201 | anaResult_syncPixVertical =>anaResult_syncPixVertical, |
202 | anaResult_frontPorchHorizontal =>anaResult_frontPorchHorizontal, |
203 | anaResult_frontPorchVertical =>anaResult_frontPorchVertical, |
204 | anaResult_backPorchHorizontal =>anaResult_backPorchHorizontal, |
205 | anaResult_backPorchVertical =>anaResult_backPorchVertical, |
206 | anaResult_syncPolarityHorizontal =>anaResult_syncPolarityHorizontal, |
207 | anaResult_syncPolarityVertical =>anaResult_syncPolarityVertical, |
208 | sel =>sel, |
209 | result_pixHorizontal =>result_pixHorizontal, |
210 | result_linesVertical =>result_linesVertical, |
211 | result_pixTotalHorizontal =>result_pixTotalHorizontal, |
212 | result_linesTotalVertical =>result_linesTotalVertical, |
213 | result_syncPixHorizontal =>result_syncPixHorizontal, |
214 | result_syncPixVertical =>result_syncPixVertical, |
215 | result_frontPorchHorizontal =>result_frontPorchHorizontal, |
216 | result_frontPorchVertical =>result_frontPorchVertical, |
217 | result_backPorchHorizontal =>result_backPorchHorizontal, |
218 | result_backPorchVertical =>result_backPorchVertical, |
219 | result_syncPolarityHorizontal =>result_syncPolarityHorizontal, |
220 | result_syncPolarityVertical =>result_syncPolarityVertical, |
221 | muxClk => muxClk |
222 | );
|
223 | |
224 | -- *** Test Bench - User Defined Section ***
|
225 | tb : process |
226 | begin
|
227 | S_Reset <= '1'; wait for resetDelay(iii); |
228 | S_Reset <= '0'; |
229 | wait; -- will wait forever |
230 | end process; |
231 | |
232 | Ck2: process |
233 | begin
|
234 | Clk_G <= '0'; wait for pixClkCycle(iii); |
235 | Clk_G <= '1'; wait for pixClkCycle(iii); |
236 | end process; |
237 | -- *** End Test Bench - User Defined Section ***
|
238 | process
|
239 | |
240 | begin
|
241 | iii <= 0; wait for 18 ms; --18ms |
242 | iii <= 2; wait for 18 ms; --18ms |
243 | iii <= 3; wait for 18 ms; --18ms |
244 | iii <= 1; wait; |
245 | end process; |
246 | |
247 | process
|
248 | |
249 | begin
|
250 | analysisHSync <= '1'; wait for 1 ms; |
251 | analysisHSync <= '0'; wait for 5 ms; |
252 | analysisVSync <= '0'; wait for 15 ms; |
253 | analysisVSync <= '1'; wait for 5 ms; |
254 | analysisDE <= '0'; wait for 1 ms; |
255 | analysisDE <= '1'; wait for 5 ms; |
256 | wait for 18 ms; |
257 | end process; |
258 | |
259 | process
|
260 | |
261 | begin
|
262 | sel <="00000001"; |
263 | wait for 1 ms; |
264 | end process; |
265 | |
266 | |
267 | end; |
Nachtrag: Ich habe eben endeckt das mir die Simulation Warnungen ausgibt:
1 | # Warning: ELAB1_0026: top_testbench.vhd : (203, 0): There is no default binding for component "top".(Port "resetFormatChange" is not on the entity). |
2 | # Warning: COMP96_0523: top_testbench.vhd : (204, 21): Signal "iii" without default value used in generic map. This may cause problems during design elaboration. |
3 | # ELBREAD: Warning: Component uut : top not bound. |
p.s. Errors gibt er aber nicht aus ;) Aber vielleicht kann mir ja jemand schon Anhand der Warnungen sagen wo mein Problem liegt. Im moment bin ich ziemlich ratlos, denn zumindest das verknüpfen der CLK-Signale sollte doch klappen(wenn man mal über die anderen Verknüpfungen beiseite lässt) Ich hoffe ich konnte mein Problem einigermaßen verständlich schildern. viele Grüße Heiko