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Forum: FPGA, VHDL & Co. Problem mit testbench , evtl. port-mapping fehler


Autor: Heiko B. (2deep)
Datum:

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Hi,

als kleines Vorwort:"Ich bin noch recht unerfahren mit VHDL"

Ich habe Desing mit mehreren Komponenten und bin gerade an dem Punkt die 
Komponenten untereinander zuverknüpfen.
Allerdings scheint es so das ich dabei Fehler mache.

Ich benutze zum entwickeln ispLever + Aldec Active HDL

Unzwar habe ich in meiner top-entity einen in-port "Clk_G".
Welchen ich in der im testbench-file auch stimuliere.
Dies wird mir auch in der Simulation angezeigt.

Nun möchte ich diesen Port(Clk_G) auf die Clk-Ports der einzelnen 
Komponenten mappen.

Allerdings werden mir die Clk-ports der Komponenten als "undefined" 
angezeigt und bleiben es auch und das obwohl der "Clk_G" unermütlich 
zwischen "1" und "0" wechselt.

Hier meine top.vhdl:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity top is
generic (ii : natural := 0);

port(
    Clk_G                : in std_logic;
    S_Reset                : in std_logic; 
    -- out-ports from the environment
    H                  : out std_logic;
    V                  : out std_logic;
    DE_out                : out std_logic;
    Re                  : out std_logic_vector (7 downto 0);
    Gr                  : out std_logic_vector (7 downto 0);
    Bl                  : out std_logic_vector (7 downto 0);
    Pixels_Tot              : inout std_logic_vector (11 downto 0);
    Lines_Tot              : inout std_logic_vector (10 downto 0);
    Pixels_Act              : out std_logic_vector (11 downto 0);
    Lines_Act              : out std_logic_vector (10 downto 0);
    Hor_sync              : out std_logic_vector (5 downto 0);
    Ver_sync              : out std_logic_vector (5 downto 0);
    Hor_F_P                : out std_logic_vector (9 downto 0);
    Hor_B_P                : out std_logic_vector (9 downto 0);
    H_sync_Pol              : out std_logic;
    Ver_F_P                : out std_logic_vector (2 downto 0);
    Ver_B_P                : out std_logic_vector (5 downto 0);
    V_sync_Pol              : out std_logic
    
  );

end;

architecture top_arch of top is
    -- buffer-signals to hand the analysis-result(aResult_) data to the mux_displayUnit(anaResult_)
    signal tempAnaResult_pixHorizontal      : std_logic_vector(11 downto 0);
    signal tempAnaResult_linesVertical      : std_logic_vector(10 downto 0);    
    signal tempAnaResult_pixTotalHorizontal    : std_logic_vector(11 downto 0);
    signal tempAnaResult_linesTotalVertical    : std_logic_vector(10 downto 0);
    signal tempAnaResult_syncPixHorizontal    : std_logic_vector(5 downto 0);
    signal tempAnaResult_syncPixVertical    : std_logic_vector(5 downto 0);
    signal tempAnaResult_frontPorchHorizontal  : std_logic_vector(9 downto 0);
    signal tempAnaResult_frontPorchVertical    : std_logic_vector(2 downto 0);
    signal tempAnaResult_backPorchHorizontal  : std_logic_vector(9 downto 0);
    signal tempAnaResult_backPorchVertical    : std_logic_vector(5 downto 0);
    signal tempAnaResult_syncPolarityHorizontal  : std_logic;
    signal tempAnaResult_syncPolarityVertical  : std_logic;
    signal sel                  : std_logic_vector(7 downto 0);
    signal du_horizontalPix            : natural;    -- active horizontal pix
    signal du_verticalLines            : natural;    -- active vertical lines
    signal du_horizontalTotalPix        : natural;    -- total horizontal pix (active pix + frontporch + etc.)
    signal du_verticalTotalLines        : natural;    -- total vertical lines (active lines + frontporch + etc.)
    signal du_horizontalSyncPix          : natural;    -- horizontal pix-size for the sync-signal
    signal du_verticalSyncPix          : natural;    -- vertical line-size for the sync-signal
    signal du_horizontalFrontPorch        : natural;    -- horizontal frontporch
    signal du_horizontalBackPorch        : natural;    -- horizontal backporch
    signal du_verticalFrontPorch        : natural;    -- vertical frontporch
    signal du_verticalBackPorch          : natural;    -- vertical backporch
    signal du_hSyncPolarity            : std_logic;    -- HSync-Polarity
    signal du_vSyncPolarity            : std_logic;    -- VSync-Polarity
    signal manual_pixHorizontal          : natural;
    signal manual_linesVertical          : natural;
    signal manual_pixTotalHorizontal      : natural;
    signal manual_linesTotalVertical      : natural;
    signal manual_syncPixHorizontal        : natural;
    signal manual_syncPixVertical        : natural;
    signal manual_frontPorchHorizontal      : natural;
    signal manual_frontPorchVertical      : natural;
    signal manual_backPorchHorizontal      : natural;
    signal manual_backPorchVertical        : natural;
    signal manual_syncPolarityHorizontal    : std_logic;
    signal manual_syncPolarityVertical      : std_logic;
    signal resetFormatChange          : std_logic;

    signal clock          : std_logic;

  
  component displayunit
  generic (i : natural := 0);
    port(
      clk            : in std_logic;
      reset          : in std_logic;
      DE            : out std_logic;
      hSync          : out std_logic;
      vSync          : out std_logic;
      R            : out std_logic_vector (7 downto 0);
      G            : out std_logic_vector (7 downto 0);
      B            : out std_logic_vector (7 downto 0);
      -- in-ports from the displayUnit
      du_horizontalPix    : in natural;    -- active horizontal pix
      du_verticalLines    : in natural;    -- active vertical lines
      du_horizontalTotalPix  : in natural;    -- total horizontal pix (active pix + frontporch + etc.)
      du_verticalTotalLines  : in natural;    -- total vertical lines (active lines + frontporch + etc.)
      du_horizontalSyncPix  : in natural;    -- horizontal pix-size for the sync-signal
      du_verticalSyncPix    : in natural;    -- vertical line-size for the sync-signal
      du_horizontalFrontPorch  : in natural;    -- horizontal frontporch
      du_horizontalBackPorch  : in natural;    -- horizontal backporch
      du_verticalFrontPorch  : in natural;    -- vertical frontporch
      du_verticalBackPorch  : in natural;    -- vertical backporch
      du_hSyncPolarity    : in std_logic;    -- HSync-Polarity
      du_vSyncPolarity    : in std_logic    -- VSync-Polarity
      );


  end component;
  signal internH, internV, internDE : std_logic;

  component analysis
    port(
      -- in-ports for the analysis(handed by the video-in-port)
      analysisClk            : in std_logic;
      analysisReset          : in std_logic;
      analysisHSync          : in std_logic;
      analysisVSync          : in std_logic;
      analysisDE            : in std_logic;
      -- out-port from analysis(signal to alert about a format-change)
      formatChange          : out std_logic;
      -- in-port from analysis(to reset the formatChange-signal)
      resetFormatChange        : in std_logic;
      -- out-ports from the analysis
      aResult_totalPix        : inout std_logic_vector (11 downto 0);
      aResult_totalLines        : inout std_logic_vector (10 downto 0);
      aResult_activePix        : out std_logic_vector (11 downto 0);
      aResult_activeLines        : out std_logic_vector (10 downto 0);
      aResult_hSync          : out std_logic_vector (5 downto 0);
      aResult_vSync          : out std_logic_vector (5 downto 0);
      aResult_horizontalFrontPorch  : out std_logic_vector (9 downto 0);
      aResult_horizontalBackPorch    : out std_logic_vector (9 downto 0);
      aResult_hSyncPolarity      : out std_logic;
      aResult_verticalFrontPorch    : out std_logic_vector (2 downto 0);
      aResult_verticalBackPorch    : out std_logic_vector (5 downto 0);
      aResult_vSyncPolarity      : out std_logic  
      );
  end component;
    
  component mux_displayUnit
    port(
      muxClk                : in std_logic;  
      -- in-port from mux_displayUnit(to select the source of format-data)
      sel                  : in std_logic_vector (7 downto 0);
      -- in-port from analysis(to reset the formatChange-signal)
      anaResult_pixHorizontal        : in std_logic_vector(11 downto 0);
      anaResult_linesVertical        : in std_logic_vector(10 downto 0);
      anaResult_pixTotalHorizontal    : in std_logic_vector(11 downto 0);
      anaResult_linesTotalVertical    : in std_logic_vector(10 downto 0);
      anaResult_syncPixHorizontal      : in std_logic_vector(5 downto 0);
      anaResult_syncPixVertical      : in std_logic_vector(5 downto 0);
      anaResult_frontPorchHorizontal    : in std_logic_vector(9 downto 0);
      anaResult_frontPorchVertical    : in std_logic_vector(2 downto 0);
      anaResult_backPorchHorizontal    : in std_logic_vector(9 downto 0);
      anaResult_backPorchVertical      : in std_logic_vector(5 downto 0);
      anaResult_syncPolarityHorizontal  : in std_logic;
      anaResult_syncPolarityVertical    : in std_logic;
      -- in-ports from mux_displayUnit(manual-input handed by the localbus)
      manual_pixHorizontal        : in natural;
      manual_linesVertical        : in natural;
      manual_pixTotalHorizontal      : in natural;
      manual_linesTotalVertical      : in natural;
      manual_syncPixHorizontal      : in natural;
      manual_syncPixVertical        : in natural;
      manual_frontPorchHorizontal      : in natural;
      manual_frontPorchVertical      : in natural;
      manual_backPorchHorizontal      : in natural;
      manual_backPorchVertical      : in natural;
      manual_syncPolarityHorizontal    : in std_logic;
      manual_syncPolarityVertical      : in std_logic;
      -- resultdata which will be handed to the displayUnit
      result_pixHorizontal        : out std_logic_vector(11 downto 0);
      result_linesVertical        : out std_logic_vector(10 downto 0);
      result_pixTotalHorizontal      : out std_logic_vector(11 downto 0);
      result_linesTotalVertical      : out std_logic_vector(10 downto 0);
      result_syncPixHorizontal      : out std_logic_vector(5 downto 0);
      result_syncPixVertical        : out std_logic_vector(5 downto 0);
      result_frontPorchHorizontal      : out std_logic_vector(9 downto 0);
      result_frontPorchVertical      : out std_logic_vector(2 downto 0);
      result_backPorchHorizontal      : out std_logic_vector(9 downto 0);
      result_backPorchVertical      : out std_logic_vector(5 downto 0);
      result_syncPolarityHorizontal    : out std_logic;
      result_syncPolarityVertical      : out std_logic
      );
  end component;

    
begin


  clock <= Clk_G ;


aa:  displayunit
  port map(
      clk              => Clk_G,
      reset            => S_Reset,
      DE              => internDE,
      hSync            => internH,
      vSync            => internV,
      R              => Re,
      G              => Gr,
      B              => Bl,
      du_horizontalPix      => du_horizontalPix,
      du_verticalLines      => du_verticalLines,
      du_horizontalTotalPix    => du_horizontalTotalPix,
      du_verticalTotalLines    => du_verticalTotalLines,
      du_horizontalSyncPix    => du_horizontalSyncPix,  
      du_verticalSyncPix      => du_verticalSyncPix,    
      du_horizontalFrontPorch    => du_horizontalFrontPorch,  
      du_horizontalBackPorch    => du_horizontalBackPorch,  
      du_verticalFrontPorch    => du_verticalFrontPorch,  
      du_verticalBackPorch    => du_verticalBackPorch,  
      du_hSyncPolarity      => du_hSyncPolarity,    
      du_vSyncPolarity      => du_vSyncPolarity    
      );

bb: analysis
  port map(
      --
      analysisClk            => Clk_G,
      analysisReset          => S_Reset,
      analysisHSync          => internH,
      analysisVSync          => internV,
      analysisDE            => internDE,
      -- out-ports(results) of analysis mapped on the buffer-signals
      aResult_totalPix        => tempAnaResult_pixTotalHorizontal,
      aResult_totalLines        => tempAnaResult_linesTotalVertical,
      aResult_activePix        => tempAnaResult_pixHorizontal,
      aResult_activeLines        => tempAnaResult_linesVertical,
      aResult_hSync          => tempAnaResult_syncPixHorizontal,
      aResult_vSync          => tempAnaResult_syncPixVertical,
      aResult_horizontalFrontPorch  => tempAnaResult_frontPorchHorizontal,
      aResult_horizontalBackPorch    => tempAnaResult_backPorchHorizontal,
      aResult_hSyncPolarity      => tempAnaResult_syncPolarityHorizontal,
      aResult_verticalFrontPorch    => tempAnaResult_frontPorchVertical,
      aResult_verticalBackPorch    => tempAnaResult_backPorchVertical,
      aResult_vSyncPolarity      => tempAnaResult_syncPolarityVertical,
    --  formatChange          => formatChange,
      resetFormatChange        => resetFormatChange
      );

cc: mux_displayUnit
  port map(
      muxClk                  => clock,
      -- in-ports from mux_displayUnit mapped on the buffer-signals
      anaResult_pixTotalHorizontal      => tempAnaResult_pixTotalHorizontal,
      anaResult_linesTotalVertical      => tempAnaResult_linesTotalVertical, 
      anaResult_pixHorizontal          => tempAnaResult_pixHorizontal,
      anaResult_linesVertical          => tempAnaResult_linesVertical,
      anaResult_syncPixHorizontal        => tempAnaResult_syncPixHorizontal,
      anaResult_syncPixVertical        => tempAnaResult_syncPixVertical,
      anaResult_frontPorchHorizontal      => tempAnaResult_frontPorchHorizontal,
      anaResult_backPorchHorizontal      => tempAnaResult_backPorchHorizontal,
      anaResult_syncPolarityHorizontal    => tempAnaResult_syncPolarityHorizontal,
      anaResult_frontPorchVertical      => tempAnaResult_frontPorchVertical,
      anaResult_backPorchVertical        => tempAnaResult_backPorchVertical,
      anaResult_syncPolarityVertical      => tempAnaResult_syncPolarityVertical,
      manual_pixHorizontal          => manual_pixHorizontal,
      manual_linesVertical          => manual_linesVertical,
      manual_pixTotalHorizontal        => manual_pixTotalHorizontal,
      manual_linesTotalVertical        => manual_linesTotalVertical,
      manual_syncPixHorizontal        => manual_syncPixHorizontal,
      manual_syncPixVertical          => manual_syncPixVertical,
      manual_frontPorchHorizontal        => manual_frontPorchHorizontal,
      manual_frontPorchVertical        => manual_frontPorchVertical,
      manual_backPorchHorizontal        => manual_backPorchHorizontal,
      manual_backPorchVertical        => manual_backPorchVertical,
      manual_syncPolarityHorizontal      => manual_syncPolarityHorizontal,
      manual_syncPolarityVertical        => manual_syncPolarityVertical,
      sel                    => sel
      );
H <= internH;
V <= internV;
DE_out <= internDE;

end top_arch;

wie man sehen kann hab ich versucht den "muxClk" über ein 
zwischensignal("clock") zu mappen. Aber auch das fürht zu keinerlei 
aktivität des "muxClk" in der Simulation.

Ein weiteres Indiz dafür das mit dem mapping was nicht stimmt ist
das wenn ich im Active-HDL(Simulation) auf das "muxClk"-signal den 
Befehl "View in Dataflow" ausführe mir keinerlei Verknüpfungen Angezeigt 
werden.

Eventuell aber ist ja auch mein Fehler in der testbench selbst zufinden 
vondaher hier:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; 
use work.formats.all;

entity testbench is
end testbench;

architecture behavior of testbench is 

  component top
  generic (ii : natural :=0);
  --generic (iii : natural :=0);
    port(
      Clk_G           : in std_logic;
      S_Reset         : in std_logic;          
      resetFormatChange    : in std_logic;
      formatChange      : out std_logic;

      anaResult_pixHorizontal        : in std_logic_vector(11 downto 0);
      anaResult_linesVertical        : in std_logic_vector(10 downto 0);
      anaResult_pixTotalHorizontal    : in std_logic_vector(11 downto 0);
      anaResult_linesTotalVertical    : in std_logic_vector(10 downto 0);
      anaResult_syncPixHorizontal      : in std_logic_vector(5 downto 0);
      anaResult_syncPixVertical      : in std_logic_vector(5 downto 0);
      anaResult_frontPorchHorizontal    : in std_logic_vector(9 downto 0);
      anaResult_frontPorchVertical    : in std_logic_vector(2 downto 0);
      anaResult_backPorchHorizontal    : in std_logic_vector(9 downto 0);
      anaResult_backPorchVertical      : in std_logic_vector(5 downto 0);
      anaResult_syncPolarityHorizontal  : in std_logic;
      anaResult_syncPolarityVertical    : in std_logic;

      analysisClk            : in std_logic;
      analysisReset          : in std_logic;
      analysisHSync          : in std_logic;
      analysisVSync          : in std_logic;
      analysisDE            : in std_logic;

      aResult_totalPix        : inout std_logic_vector (11 downto 0);
      aResult_totalLines        : inout std_logic_vector (10 downto 0);
      aResult_activePix        : out std_logic_vector (11 downto 0);
      aResult_activeLines        : out std_logic_vector (10 downto 0);
      aResult_hSync          : out std_logic_vector (5 downto 0);
      aResult_vSync          : out std_logic_vector (5 downto 0);
      aResult_horizontalFrontPorch  : out std_logic_vector (9 downto 0);
      aResult_horizontalBackPorch    : out std_logic_vector (9 downto 0);
      aResult_hSyncPolarity      : out std_logic;
      aResult_verticalFrontPorch    : out std_logic_vector (2 downto 0);
      aResult_verticalBackPorch    : out std_logic_vector (5 downto 0);
      aResult_vSyncPolarity      : out std_logic;

      muxClk                : in std_logic;

      sel                  : in std_logic_vector (7 downto 0);

      result_pixHorizontal        : out std_logic_vector(11 downto 0);
      result_linesVertical        : out std_logic_vector(10 downto 0);
      result_pixTotalHorizontal      : out std_logic_vector(11 downto 0);
      result_linesTotalVertical      : out std_logic_vector(10 downto 0);
      result_syncPixHorizontal      : out std_logic_vector(5 downto 0);
      result_syncPixVertical        : out std_logic_vector(5 downto 0);
      result_frontPorchHorizontal      : out std_logic_vector(9 downto 0);
      result_frontPorchVertical      : out std_logic_vector(2 downto 0);
      result_backPorchHorizontal      : out std_logic_vector(9 downto 0);
      result_backPorchVertical      : out std_logic_vector(5 downto 0);
      result_syncPolarityHorizontal    : out std_logic;
      result_syncPolarityVertical      : out std_logic;

      H             : out std_logic;
      V             : out std_logic;
      DE_out           : out std_logic;
      Pixels_Act        : out std_logic_vector (11 downto 0);
      Lines_Act        : out std_logic_vector (10 downto 0);
      Hor_sync        : out std_logic_vector (5 downto 0);
      Ver_sync        : out std_logic_vector (5 downto 0);
      Re            : out std_logic_vector (7 downto 0);
      Gr             : out std_logic_vector (7 downto 0);
      Bl             : out std_logic_vector (7 downto 0);
      Hor_F_P          : out std_logic_vector (9 downto 0);
      Hor_B_P          : out std_logic_vector (9 downto 0);
      H_sync_Pol        : out std_logic;
      Ver_F_P          : out std_logic_vector (2 downto 0);
      Ver_B_P          : out std_logic_vector (5 downto 0);
      V_sync_Pol        : out std_logic;
      Pixels_Tot        : inout std_logic_vector (11 downto 0);
      Lines_Tot        : inout std_logic_vector (10 downto 0)
      );
  end component;

  signal Clk_G           : std_logic;
  signal S_Reset           : std_logic;
  signal H             : std_logic;
  signal V             : std_logic;
  signal DE_out          : std_logic;
  signal Pixels_Tot        : std_logic_vector (11 downto 0);
  signal Lines_Tot        : std_logic_vector (10 downto 0);
  signal Pixels_Act        : std_logic_vector (11 downto 0);
  signal Lines_Act        : std_logic_vector (10 downto 0);
  signal Hor_sync          : std_logic_vector (5 downto 0);
  signal Ver_sync          : std_logic_vector (5 downto 0);
  signal Re             : std_logic_vector (7 downto 0);
  signal Gr             : std_logic_vector (7 downto 0);
  signal Bl             : std_logic_vector (7 downto 0);
  signal Hor_F_P          : std_logic_vector (9 downto 0);
  signal Hor_B_P          : std_logic_vector (9 downto 0);
  signal H_sync_Pol        : std_logic;
  signal Ver_F_P          : std_logic_vector (2 downto 0);
  signal Ver_B_P          : std_logic_vector (5 downto 0);
  signal V_sync_Pol        : std_logic;
  signal resetFormatChange    : std_logic;
  signal formatChange        : std_logic;
  signal iii             : natural;
  signal du_horizontalPix      : natural;    -- active horizontal pix
  signal du_verticalLines      : natural;    -- active vertical lines
  signal du_horizontalTotalPix  : natural;    -- total horizontal pix (active pix + frontporch + etc.)
  signal du_verticalTotalLines  : natural;    -- total vertical lines (active lines + frontporch + etc.)
  signal du_horizontalSyncPix    : natural;    -- horizontal pix-size for the sync-signal
  signal du_verticalSyncPix    : natural;    -- vertical line-size for the sync-signal
  signal du_horizontalFrontPorch  : natural;    -- horizontal frontporch
  signal du_horizontalBackPorch  : natural;    -- horizontal backporch
  signal du_verticalFrontPorch  : natural;    -- vertical frontporch
  signal du_verticalBackPorch    : natural;    -- vertical backporch
  signal du_hSyncPolarity      : std_logic;  -- HSync-Polarity
  signal du_vSyncPolarity      : std_logic;  -- VSync-Polarity

  signal analysisHSync          : std_logic;
  signal analysisVSync          : std_logic;
  signal analysisDE            : std_logic;
  signal analysisClk            : std_logic;
  signal analysisReset          : std_logic;

  signal anaResult_pixHorizontal        : std_logic_vector(11 downto 0);
  signal anaResult_linesVertical        : std_logic_vector(10 downto 0);
  signal anaResult_pixTotalHorizontal      : std_logic_vector(11 downto 0);
  signal anaResult_linesTotalVertical      : std_logic_vector(10 downto 0);
  signal anaResult_syncPixHorizontal      : std_logic_vector(5 downto 0);
  signal anaResult_syncPixVertical      : std_logic_vector(5 downto 0);
  signal anaResult_frontPorchHorizontal    : std_logic_vector(9 downto 0);
  signal anaResult_frontPorchVertical      : std_logic_vector(2 downto 0);
  signal anaResult_backPorchHorizontal    : std_logic_vector(9 downto 0);
  signal anaResult_backPorchVertical      : std_logic_vector(5 downto 0);
  signal anaResult_syncPolarityHorizontal    : std_logic;
  signal anaResult_syncPolarityVertical    : std_logic;
  
  signal sel                  : std_logic_vector (7 downto 0);

  signal result_pixHorizontal          : std_logic_vector(11 downto 0);
  signal result_linesVertical          : std_logic_vector(10 downto 0);
  signal result_pixTotalHorizontal      : std_logic_vector(11 downto 0);
  signal result_linesTotalVertical      : std_logic_vector(10 downto 0);
  signal result_syncPixHorizontal        : std_logic_vector(5 downto 0);
  signal result_syncPixVertical        : std_logic_vector(5 downto 0);
  signal result_frontPorchHorizontal      : std_logic_vector(9 downto 0);
  signal result_frontPorchVertical      : std_logic_vector(2 downto 0);
  signal result_backPorchHorizontal      : std_logic_vector(9 downto 0);
  signal result_backPorchVertical        : std_logic_vector(5 downto 0);
  signal result_syncPolarityHorizontal    : std_logic;
  signal result_syncPolarityVertical      : std_logic;
  signal muxClk                : std_logic;



begin

-- Please check and add your generic clause manually
  uut: top 
  generic map (ii => iii) 
    port map(
        Clk_G           => Clk_G,
        S_Reset         => S_Reset,
        H             => H,
        V            => V,
        DE_out          => DE_out,
        Pixels_Tot        => Pixels_Tot,
        Lines_Tot        => Lines_Tot,
        Pixels_Act        => Pixels_Act,
        Lines_Act        => Lines_Act,
        Hor_sync        => Hor_sync,
        Ver_sync        => Ver_sync,
        Re             => Re,
        Gr             => Gr,
        Bl             => Bl,
        Hor_F_P          => Hor_F_P,
        Hor_B_P          => Hor_B_P,
        H_sync_Pol        => H_sync_Pol,
        Ver_F_P          => Ver_F_P,
        Ver_B_P          => Ver_B_P,
        V_sync_Pol        => V_sync_Pol,
        resetFormatChange    => resetFormatChange,
        formatChange      => formatChange,
        analysisClk        => analysisClk,
        analysisReset      => analysisReset,
        analysisHSync      => analysisHSync,
        analysisVSync      => analysisVSync,
        analysisDE        => analysisDE,
        anaResult_pixHorizontal        =>anaResult_pixHorizontal,
        anaResult_linesVertical        =>anaResult_linesVertical,
        anaResult_pixTotalHorizontal    =>anaResult_pixTotalHorizontal,
        anaResult_linesTotalVertical    =>anaResult_linesTotalVertical,
        anaResult_syncPixHorizontal      =>anaResult_syncPixHorizontal,
        anaResult_syncPixVertical      =>anaResult_syncPixVertical,
        anaResult_frontPorchHorizontal    =>anaResult_frontPorchHorizontal,
        anaResult_frontPorchVertical    =>anaResult_frontPorchVertical,
        anaResult_backPorchHorizontal    =>anaResult_backPorchHorizontal,
        anaResult_backPorchVertical      =>anaResult_backPorchVertical,
        anaResult_syncPolarityHorizontal  =>anaResult_syncPolarityHorizontal,
        anaResult_syncPolarityVertical    =>anaResult_syncPolarityVertical,
        sel                  =>sel,
        result_pixHorizontal        =>result_pixHorizontal,
        result_linesVertical        =>result_linesVertical,
        result_pixTotalHorizontal      =>result_pixTotalHorizontal,
        result_linesTotalVertical      =>result_linesTotalVertical,
        result_syncPixHorizontal      =>result_syncPixHorizontal,
        result_syncPixVertical        =>result_syncPixVertical,
        result_frontPorchHorizontal      =>result_frontPorchHorizontal,
        result_frontPorchVertical      =>result_frontPorchVertical,
        result_backPorchHorizontal      =>result_backPorchHorizontal,
        result_backPorchVertical      =>result_backPorchVertical,
        result_syncPolarityHorizontal    =>result_syncPolarityHorizontal,
        result_syncPolarityVertical      =>result_syncPolarityVertical,
        muxClk                => muxClk 
        );

-- *** Test Bench - User Defined Section ***
   tb : process
   begin
    S_Reset <= '1'; wait for resetDelay(iii);
    S_Reset <= '0';
      wait; -- will wait forever
   end process;

  Ck2: process
  begin
    Clk_G <= '0'; wait for pixClkCycle(iii);
    Clk_G <= '1'; wait for pixClkCycle(iii);
  end process;
-- *** End Test Bench - User Defined Section ***
  process

    begin
      iii <= 0; wait for 18 ms; --18ms
      iii <= 2; wait for 18 ms; --18ms
      iii <= 3; wait for 18 ms; --18ms
      iii <= 1; wait;
  end process;

  process

    begin
      analysisHSync    <= '1'; wait for 1 ms;
      analysisHSync    <= '0'; wait for 5 ms;    
      analysisVSync    <= '0'; wait for 15 ms;
      analysisVSync    <= '1'; wait for 5 ms;
      analysisDE      <= '0'; wait for 1 ms;
      analysisDE      <= '1'; wait for 5 ms;
      wait for 18 ms;
  end process;
  
  process
    
    begin
      sel                <="00000001";
      wait for 1 ms;
  end process;


end;


Nachtrag:
Ich habe eben endeckt das mir die Simulation Warnungen ausgibt:
# Warning: ELAB1_0026: top_testbench.vhd : (203, 0): There is no default binding for component "top".(Port "resetFormatChange" is not on the entity).
# Warning: COMP96_0523: top_testbench.vhd : (204, 21): Signal "iii" without default value used in generic map. This may cause problems during design elaboration.
# ELBREAD: Warning: Component uut : top not bound.

p.s. Errors gibt er aber nicht aus ;)
Aber vielleicht kann mir ja jemand schon Anhand der Warnungen sagen wo 
mein Problem liegt.

Im moment bin ich ziemlich ratlos, denn zumindest das verknüpfen der 
CLK-Signale sollte doch klappen(wenn man mal über die anderen 
Verknüpfungen beiseite lässt)

Ich hoffe ich konnte mein Problem einigermaßen verständlich schildern.

viele Grüße

Heiko

Autor: Duke Scarring (Gast)
Datum:

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Huch, bei den vielen Signalen siehst Du noch durch?
Ich würde dafür records verwenden...

Zu Deinem Problem:
Deine Component (top) und Deine Testbench passen nicht zusammen (not 
bound). In Deiner Simulation gibt es also gar kein top.

Und da steht ja auch der Grund: Port "resetFormatChange" is not on the 
entity

Dank records sehen meine entity/component-Sachen sehr übersichtlich aus:
entity beispiel is
  port(
    clk    : in  std_logic;
    rst_n  : in  std_logic;
    data_i : in  data_i_t;
    data_o : out data_o_t
  );
end entity beispiel;

Duke

Autor: berndl (Gast)
Datum:

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Hi,

und ein weiterer Punkt (ohne mich duch die ganzen Zeilen gequaelt zu 
haben): Du hast Components instanziiert, die inout ports haben. Das 
moegen manche Tools und Simulatoren nicht. Da hilft eine einfache 
Zuweisung vom internen/externen Signal auf deinen inout port.

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