Hallo ich habe eine Verständnisfrage, wahrscheinlich liegt das nur and der Ausdrucksweise meines Professors. Das folgende ist die Aufgabenstellung, Punkt 1 und 2 habe ich erledigt. Punkt drei verstehe ich allerdings nicht. Kann man in einem VHDL-file mehrere Arch/Entity haben die aber teilweise auch mit den selben Signalen arbeitet. b. hierarchische Implementierung des Memory‐Controlers: 1. Erstellen Sie eine zweite Architektur für Ihren Memory‐Controler in einer separaten VHDL-Datei! 2. Separieren Sie den Adresspfad(data_reg, src_readdata_p, data_b_p) in einen VHDL‐Block! 3. Separieren Sie den Datenpfad in eine Entity/Architecture! Source-Code: ----------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.test_pack.all; entity sram_controler is port( clk_i : in std_ulogic; reset_n_i : in std_ulogic; audio_data_i : in std_ulogic_vector(23 downto 0); srctr_data_o : out std_ulogic_vector(23 downto 0); fsm_start_addr_i : in std_ulogic_vector(18 downto 0); fsm_we_i : in std_ulogic; fsm_re_i : in std_ulogic; srctr_idle_o : out std_ulogic; srctr_end_addr_plus1_o : out std_ulogic_vector(18 downto 0); srctr_we_reg_n_o : out std_ulogic; srctr_ce_reg_n_o : out std_ulogic; srctr_oe_reg_n_o : out std_ulogic; srctr_lb_reg_n_o : out std_ulogic; srctr_ub_reg_n_o : out std_ulogic; srctr_addr_reg_o : out std_ulogic_vector(18 downto 0); mem_data_b : inout std_logic_vector(15 downto 0)); signal state : fsm_t; signal addr_next : std_ulogic_vector(18 downto 0); signal addr_inc : std_ulogic_vector(18 downto 0); signal addr_reg : std_ulogic_vector(18 downto 0); signal data_reg : std_ulogic_vector(23 downto 0); end sram_controler; architecture sep_arch of sram_controler is begin ------------------------------------------------------------------------ --- -- p_fsm ------------------------------------------------------------------------ --- p_fsm: process (clk_i, reset_n_i) begin if reset_n_i = '0' then state <= FSM_IDLE; --if reset, set state idle elsif clk_i'event and clk_i = '1' then --with next rising flank... case state is when FSM_IDLE => --define condition for the next state if fsm_re_i = '1' and fsm_we_i = '0' then state <= FSM_READ_MEM_1; elsif fsm_we_i = '1' then state <= FSM_WRITE_MEM_1; elsif fsm_we_i = '0' and fsm_re_i = '0' then state <= FSM_IDLE; end if; when FSM_READ_MEM_1 => --define condition for next state state <= FSM_READ_MEM_2; when FSM_READ_MEM_2 => --define condition for next state state <= FSM_READ_MEM_3; when FSM_READ_MEM_3 => --define condition for next state if fsm_we_i = '1' then state <= FSM_WRITE_MEM_1; elsif fsm_re_i = '1' and fsm_we_i = '0' then state <= FSM_READ_MEM_1; elsif fsm_re_i = '0' and fsm_we_i = '0' then state <= FSM_IDLE; end if; when FSM_WRITE_MEM_1 => --define condition for next state state <= FSM_WRITE_MEM_2; when FSM_WRITE_MEM_2 => --define condition for next state state <= FSM_WRITE_MEM_3; when FSM_WRITE_MEM_3 => --define condition for next state if fsm_we_i = '1' then state <= FSM_WRITE_MEM_1; elsif fsm_re_i = '1' and fsm_we_i = '0' then state <= FSM_READ_MEM_1; elsif fsm_we_i = '0' and fsm_re_i = '0' then state <= FSM_IDLE; end if; when others => null; --define condition for undefine state end case; end if; end process p_fsm; ------------------------------------------------------------------------ --- -- srctr_idle_p ------------------------------------------------------------------------ --- srctr_idle_p: process (state) begin case state is when FSM_IDLE|FSM_WRITE_MEM_3|FSM_READ_MEM_3 => srctr_idle_o <= '1'; --activate the idle-output signal when others => srctr_idle_o <= '0'; --deactivate the idle-output signal end case; end process srctr_idle_p; ------------------------------------------------------------------------ --- -- control_p ------------------------------------------------------------------------ --- control_p: process (clk_i, reset_n_i) begin if reset_n_i = '0' then srctr_we_reg_n_o <= '1'; --if reset, deactivate write-enable srctr_ce_reg_n_o <= '1'; --if reset, deactivate chip-enable srctr_oe_reg_n_o <= '1'; --if reset, deactivate output-enable srctr_ub_reg_n_o <= '1'; --if reset, deactivate upper-byte srctr_lb_reg_n_o <= '0'; --if reset, deactivate lower-byte elsif clk_i'event and clk_i = '1' then --with next rising flank... srctr_lb_reg_n_o <= addr_next(0); --define lower-byte srctr_ub_reg_n_o <= not addr_next(0); --define upper-byte srctr_ce_reg_n_o <= '0'; case state is when FSM_READ_MEM_1 | FSM_READ_MEM_2 => --generate control signals srctr_we_reg_n_o <= '1'; srctr_oe_reg_n_o <= '0'; when FSM_WRITE_MEM_1 | FSM_WRITE_MEM_2 => --generate control signals srctr_we_reg_n_o <= '0'; srctr_oe_reg_n_o <= '1'; when FSM_IDLE | FSM_READ_MEM_3 | FSM_WRITE_MEM_3=> --generate control signals if fsm_we_i = '1' then srctr_we_reg_n_o <= '0'; srctr_oe_reg_n_o <= '1'; elsif fsm_re_i = '1' then srctr_we_reg_n_o <= '1'; srctr_oe_reg_n_o <= '0'; else srctr_we_reg_n_o <= '1'; srctr_oe_reg_n_o <= '1'; end if; end case; end if; end process control_p; ------------------------------------------------------------------------ --- -- datareg_p ------------------------------------------------------------------------ --- datareg_p : process (clk_i, reset_n_i) begin if reset_n_i = '0' then data_reg <= (others => '0'); --if reset, set data_reg to 0 elsif clk_i'event and clk_i = '1' then case state is when FSM_WRITE_MEM_1 => --shift register data_reg(7 downto 0) <= data_reg(15 downto 8); data_reg(15 downto 8) <= data_reg(23 downto 16); data_reg(23 downto 16) <= data_reg(7 downto 0); when FSM_WRITE_MEM_2 => --shift register data_reg(7 downto 0) <= data_reg(15 downto 8); data_reg(15 downto 8) <= data_reg(23 downto 16); data_reg(23 downto 16) <= data_reg(7 downto 0); when FSM_WRITE_MEM_3 => --write-request --transfer audio_in to data_reg if fsm_we_i = '1' then data_reg <= audio_data_i; end if; when FSM_READ_MEM_1 => --transfer byte0 or byte1 from mem_data to data_reg if addr_reg(0) = '0' then data_reg(23 downto 16) <= to_stdulogicvector(mem_data_b(7 downto 0)); else data_reg(23 downto 16) <= to_stdulogicvector(mem_data_b(15 downto 8)); end if; when FSM_READ_MEM_2 => --transfer byte0 or byte1 from mem_data to data_reg data_reg(15 downto 8) <= data_reg(23 downto 16); --shift register if addr_reg(0) = '0' then data_reg(23 downto 16) <= to_stdulogicvector(mem_data_b(7 downto 0)); else data_reg(23 downto 16) <= to_stdulogicvector(mem_data_b(15 downto 8)); end if; when FSM_READ_MEM_3 => if fsm_we_i = '1' then data_reg <= audio_data_i; else data_reg(7 downto 0) <= data_reg(15 downto 8); --shift register data_reg(15 downto 8) <= data_reg(23 downto 16); --shift register if addr_reg(0) = '0' then --transfer byte0 or byte1 from mem_data to data_reg data_reg(23 downto 16) <= to_stdulogicvector(mem_data_b(7 downto 0)); else data_reg(23 downto 16) <= to_stdulogicvector(mem_data_b(15 downto 8)); end if; end if; when FSM_IDLE => --write-request --transfer audio_in to data_reg if fsm_we_i = '1' then data_reg <= audio_data_i; end if; end case; end if; end process datareg_p ; ------------------------------------------------------------------------ --- -- src_readdata_p ------------------------------------------------------------------------ --- src_readdata_p: process (addr_reg, state, mem_data_b, data_reg) begin srctr_data_o(15 downto 0) <= data_reg(23 downto 8); --transfer data_reg byte2 to srctr_data_o byte1 case state is when FSM_READ_MEM_3 => if addr_reg(0) = '0' then --if mem_data_b(15 downto 8) = "00000000" then srctr_data_o(23 downto 16) <= to_stdulogicvector(mem_data_b(7 downto 0)); --transfer mem_data_b byte0 to srctr_data_o byte2 else srctr_data_o(23 downto 16) <= to_stdulogicvector(mem_data_b(15 downto 8)); --transfer mem_data_b byte1 to srctr_data_o byte2 end if; when others => srctr_data_o <= data_reg; --transfer data_reg to srctr_data_o end case; end process src_readdata_p; ------------------------------------------------------------------------ --- -- data_b_p ------------------------------------------------------------------------ --- data_b_p : process (state, data_reg) begin case state is when FSM_WRITE_MEM_1 | FSM_WRITE_MEM_2 | FSM_WRITE_MEM_3 => mem_data_b(7 downto 0) <= to_stdlogicvector(data_reg(7 downto 0)); --transfer data_reg byte0 to mem_data_b byte0 mem_data_b(15 downto 8) <= to_stdlogicvector(data_reg(7 downto 0)); --transfer data_reg byte0 to mem_data_b byte1 when others => mem_data_b <= (others => 'Z'); --high impedance if not in Write-Mode end case; end process data_b_p ; srctr_end_addr_plus1_o <= addr_inc; --transfer addr_inc to srctr_end_addr_plus1_o srctr_addr_reg_o <= addr_reg; --transfer addr_reg to srctr_addr_reg_o ------------------------------------------------------------------------ --- -- Adresspfad_Block ------------------------------------------------------------------------ --- adresspfad_b : block begin ------------------------------------------------------------------------ --- -- addr_next_p ------------------------------------------------------------------------ --- adr_next_p: process (state, fsm_re_i, fsm_we_i, addr_inc, fsm_start_addr_i, addr_reg) begin case state is when FSM_WRITE_MEM_1 | FSM_READ_MEM_1 | FSM_WRITE_MEM_2 | FSM_READ_MEM_2 => addr_next <= addr_inc; --set addr_next equal addr_inc when FSM_WRITE_MEM_3 | FSM_READ_MEM_3 | FSM_IDLE=> if fsm_we_i = '1' or fsm_re_i = '1' then addr_next <= fsm_start_addr_i; --if write or read-request set --fsm_start_addr_i equal addr_next else addr_next <= addr_reg; end if; end case; end process adr_next_p; ------------------------------------------------------------------------ --- -- adder_p ------------------------------------------------------------------------ --- addr_inc <= to_stdulogicvector(std_logic_vector(unsigned(addr_reg) + 1)); ------------------------------------------------------------------------ --- -- addr_count_p ------------------------------------------------------------------------ --- addr_count_p : process (clk_i, reset_n_i ) begin if reset_n_i = '0' then addr_reg <= (others => '1'); --if reset, set addr_reg to 1 elsif clk_i'event and clk_i = '1' then --with next rising flank... addr_reg <= addr_next; --addr_next pass to addr_reg end if; end process addr_count_p; end block adresspfad_b; end sep_arch; ------------------------------------------------------------------------ --- Falls einer ne Idee hat, immer her damit. Schonmal schönen Dank. Gruß Crouch
srry, so sollte die Aufgabenstellung aussehen: b. hierarchische Implementierung des Memory‐Controlers: 1. Erstellen Sie eine zweite Architektur für Ihren Memory‐Controler in einer separaten VHDL-Datei! 2. Separieren Sie den Adresspfad in einen VHDL‐Block! 3. Separieren Sie den Datenpfad(data_reg, src_readdata_p, data_b_p) in eine Entity/Architecture!
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