1 | LIBRARY ieee;
|
2 | USE ieee.std_logic_1164.ALL;
|
3 | USE ieee.std_logic_unsigned.all;
|
4 | USE ieee.numeric_std.ALL;
|
5 |
|
6 | ENTITY FLASH_BRAM_BENCH_16 IS
|
7 | END FLASH_BRAM_BENCH_16;
|
8 |
|
9 | ARCHITECTURE behavior OF FLASH_BRAM_BENCH_16 IS
|
10 |
|
11 | -- Component Declaration for the Unit Under Test (UUT)
|
12 |
|
13 | COMPONENT FLASH_CONTROLLER
|
14 | PORT(
|
15 | DA_H : OUT std_logic_vector(7 downto 0);
|
16 | DA_L : OUT std_logic_vector(7 downto 0);
|
17 | DATA_EN_H : OUT std_logic;
|
18 | DATA_EN_L : OUT std_logic;
|
19 | BYTE_SR : OUT std_logic;
|
20 | ADD_ZE : OUT std_logic;
|
21 | ADD_K_VOLL : OUT std_logic;
|
22 | ADD_EN : OUT std_logic;
|
23 | ADD_D_VOLL : OUT std_logic;
|
24 | FL_DURCHLAUF_ADD : OUT std_logic_vector(14 downto 0);
|
25 | FL_ADD_DURCHLAUF_ZERO : OUT std_logic;
|
26 | BRAM_WR_RD_ENABLE : OUT std_logic;
|
27 | BRAM_WR_RD_DISABLE : OUT std_logic;
|
28 | BRAM_R_ADD_COUNT_ENABLE : OUT std_logic;
|
29 | BRAM_R_ADD_COUNT_VOLL : OUT std_logic;
|
30 | BRAM_R_ADD : OUT std_logic_vector(13 downto 0);
|
31 | BRAM_R_ADD_ZERO : OUT std_logic;
|
32 | BRAM_CLK_1 : OUT std_logic;
|
33 | BRAM_A_1 : OUT std_logic_vector(13 downto 0);
|
34 | BRAM_IN_DA_1 : OUT std_logic_vector(11 downto 0);
|
35 | BRAM_OUT_DA_1 : OUT std_logic_vector(11 downto 0);
|
36 | BRAM_WR_ENABLE_1 : OUT std_logic_vector(0 downto 0);
|
37 | BRAM_CLK_2 : OUT std_logic;
|
38 | BRAM_A_2 : OUT std_logic_vector(13 downto 0);
|
39 | BRAM_IN_DA_2 : OUT std_logic_vector(11 downto 0);
|
40 | BRAM_OUT_DA_2 : OUT std_logic_vector(11 downto 0);
|
41 | BRAM_WR_ENABLE_2 : OUT std_logic_vector(0 downto 0);
|
42 | DA_FROM_FLASH : OUT std_logic_vector(11 downto 0);
|
43 | BADD : OUT std_logic_vector(13 downto 0);
|
44 | AUSGABE_AN_DA_WANDLER_CLK : IN std_logic;
|
45 | FLASH_ENABLE : IN std_logic;
|
46 | FLASH_RESET : IN std_logic;
|
47 | FLASH_CLK : IN std_logic;
|
48 | FLASH_ADDRESS : OUT std_logic_vector(23 downto 0);
|
49 | FLASH_RP : OUT std_logic;
|
50 | FLASH_CE : OUT std_logic;
|
51 | FLASH_OE : OUT std_logic;
|
52 | STORED_FLASH_DATA : IN std_logic_vector(7 downto 0);
|
53 | AUSGABE_DATEN_BRAM : OUT std_logic_vector(11 downto 0);
|
54 | AUSGABE_DATEN_FLASH : OUT std_logic_vector(11 downto 0)
|
55 | );
|
56 | END COMPONENT;
|
57 |
|
58 |
|
59 | --Inputs
|
60 | signal AUSGABE_AN_DA_WANDLER_CLK : std_logic := '0';
|
61 | signal FLASH_ENABLE : std_logic := '0';
|
62 | signal FLASH_RESET : std_logic := '0';
|
63 | signal FLASH_CLK : std_logic := '0';
|
64 | signal STORED_FLASH_DATA : std_logic_vector(7 downto 0) := (others => '0');
|
65 |
|
66 | --Outputs
|
67 | signal DA_H : std_logic_vector(7 downto 0);
|
68 | signal DA_L : std_logic_vector(7 downto 0);
|
69 | signal DATA_EN_H : std_logic;
|
70 | signal DATA_EN_L : std_logic;
|
71 | signal BYTE_SR : std_logic;
|
72 | signal ADD_ZE : std_logic;
|
73 | signal ADD_K_VOLL : std_logic;
|
74 | signal ADD_EN : std_logic;
|
75 | signal ADD_D_VOLL : std_logic;
|
76 | signal FL_DURCHLAUF_ADD : std_logic_vector(14 downto 0);
|
77 | signal FL_ADD_DURCHLAUF_ZERO : std_logic;
|
78 | signal BRAM_WR_RD_ENABLE : std_logic;
|
79 | signal BRAM_WR_RD_DISABLE : std_logic;
|
80 | signal BRAM_R_ADD_COUNT_ENABLE : std_logic;
|
81 | signal BRAM_R_ADD_COUNT_VOLL : std_logic;
|
82 | signal BRAM_R_ADD : std_logic_vector(13 downto 0);
|
83 | signal BRAM_R_ADD_ZERO : std_logic;
|
84 | signal BRAM_CLK_1 : std_logic;
|
85 | signal BRAM_A_1 : std_logic_vector(13 downto 0);
|
86 | signal BRAM_IN_DA_1 : std_logic_vector(11 downto 0);
|
87 | signal BRAM_OUT_DA_1 : std_logic_vector(11 downto 0);
|
88 | signal BRAM_WR_ENABLE_1 : std_logic_vector(0 downto 0);
|
89 | signal BRAM_CLK_2 : std_logic;
|
90 | signal BRAM_A_2 : std_logic_vector(13 downto 0);
|
91 | signal BRAM_IN_DA_2 : std_logic_vector(11 downto 0);
|
92 | signal BRAM_OUT_DA_2 : std_logic_vector(11 downto 0);
|
93 | signal BRAM_WR_ENABLE_2 : std_logic_vector(0 downto 0);
|
94 | signal DA_FROM_FLASH : std_logic_vector(11 downto 0);
|
95 | signal BADD : std_logic_vector(13 downto 0);
|
96 | signal FLASH_ADDRESS : std_logic_vector(23 downto 0);
|
97 | signal FLASH_RP : std_logic;
|
98 | signal FLASH_CE : std_logic;
|
99 | signal FLASH_OE : std_logic;
|
100 | signal AUSGABE_DATEN_BRAM : std_logic_vector(11 downto 0);
|
101 | signal AUSGABE_DATEN_FLASH : std_logic_vector(11 downto 0);
|
102 |
|
103 | -- Clock period definitions
|
104 | constant AUSGABE_AN_DA_WANDLER_CLK_period : time := 50000 ps; -- DIESE HIER!!
|
105 | constant FLASH_CLK_period : time := 25000 ps; -- UND DIESE HIER!!!
|
106 |
|
107 | BEGIN
|
108 |
|
109 | -- Instantiate the Unit Under Test (UUT)
|
110 | uut: FLASH_CONTROLLER PORT MAP (
|
111 | DA_H => DA_H,
|
112 | DA_L => DA_L,
|
113 | DATA_EN_H => DATA_EN_H,
|
114 | DATA_EN_L => DATA_EN_L,
|
115 | BYTE_SR => BYTE_SR,
|
116 | ADD_ZE => ADD_ZE,
|
117 | ADD_K_VOLL => ADD_K_VOLL,
|
118 | ADD_EN => ADD_EN,
|
119 | ADD_D_VOLL => ADD_D_VOLL,
|
120 | FL_DURCHLAUF_ADD => FL_DURCHLAUF_ADD,
|
121 | FL_ADD_DURCHLAUF_ZERO => FL_ADD_DURCHLAUF_ZERO,
|
122 | BRAM_WR_RD_ENABLE => BRAM_WR_RD_ENABLE,
|
123 | BRAM_WR_RD_DISABLE => BRAM_WR_RD_DISABLE,
|
124 | BRAM_R_ADD_COUNT_ENABLE => BRAM_R_ADD_COUNT_ENABLE,
|
125 | BRAM_R_ADD_COUNT_VOLL => BRAM_R_ADD_COUNT_VOLL,
|
126 | BRAM_R_ADD => BRAM_R_ADD,
|
127 | BRAM_R_ADD_ZERO => BRAM_R_ADD_ZERO,
|
128 | BRAM_CLK_1 => BRAM_CLK_1,
|
129 | BRAM_A_1 => BRAM_A_1,
|
130 | BRAM_IN_DA_1 => BRAM_IN_DA_1,
|
131 | BRAM_OUT_DA_1 => BRAM_OUT_DA_1,
|
132 | BRAM_WR_ENABLE_1 => BRAM_WR_ENABLE_1,
|
133 | BRAM_CLK_2 => BRAM_CLK_2,
|
134 | BRAM_A_2 => BRAM_A_2,
|
135 | BRAM_IN_DA_2 => BRAM_IN_DA_2,
|
136 | BRAM_OUT_DA_2 => BRAM_OUT_DA_2,
|
137 | BRAM_WR_ENABLE_2 => BRAM_WR_ENABLE_2,
|
138 | DA_FROM_FLASH => DA_FROM_FLASH,
|
139 | BADD => BADD,
|
140 | AUSGABE_AN_DA_WANDLER_CLK => AUSGABE_AN_DA_WANDLER_CLK,
|
141 | FLASH_ENABLE => FLASH_ENABLE,
|
142 | FLASH_RESET => FLASH_RESET,
|
143 | FLASH_CLK => FLASH_CLK,
|
144 | FLASH_ADDRESS => FLASH_ADDRESS,
|
145 | FLASH_RP => FLASH_RP,
|
146 | FLASH_CE => FLASH_CE,
|
147 | FLASH_OE => FLASH_OE,
|
148 | STORED_FLASH_DATA => STORED_FLASH_DATA,
|
149 | AUSGABE_DATEN_BRAM => AUSGABE_DATEN_BRAM,
|
150 | AUSGABE_DATEN_FLASH => AUSGABE_DATEN_FLASH
|
151 | );
|
152 |
|
153 | -- Clock process definitions
|
154 | AUSGABE_AN_DA_WANDLER_CLK_process :process
|
155 | begin
|
156 | AUSGABE_AN_DA_WANDLER_CLK <= '0';
|
157 | wait for AUSGABE_AN_DA_WANDLER_CLK_period/2;
|
158 | AUSGABE_AN_DA_WANDLER_CLK <= '1';
|
159 | wait for AUSGABE_AN_DA_WANDLER_CLK_period/2;
|
160 | end process;
|
161 |
|
162 | FLASH_CLK_process :process
|
163 | begin
|
164 | FLASH_CLK <= '0';
|
165 | wait for FLASH_CLK_period/2;
|
166 | FLASH_CLK <= '1';
|
167 | wait for FLASH_CLK_period/2;
|
168 | end process;
|
169 |
|
170 |
|
171 | -- Stimulus process
|
172 | stim_proc: process
|
173 | begin
|
174 | FLASH_RESET <= '1';
|
175 | FLASH_ENABLE <= '0';
|
176 | wait for 500000 ns;
|
177 | FLASH_RESET <= '0';
|
178 | FLASH_ENABLE <= '0';
|
179 | wait for 500000 ns;
|
180 | -----------------
|
181 | FLASH_RESET <= '0';
|
182 | FLASH_ENABLE <= '1';
|
183 | wait for 1000000 ns;
|
184 | FLASH_RESET <= '0';
|
185 | FLASH_ENABLE <= '0';
|
186 | wait for 800000 ns;
|
187 | ---------------------
|
188 | FLASH_RESET <= '0';
|
189 | FLASH_ENABLE <= '1';
|
190 | wait for 1000000 ns;
|
191 | FLASH_RESET <= '0';
|
192 | FLASH_ENABLE <= '0';
|
193 | wait for 500000 ns;
|
194 | ---------------------
|
195 | FLASH_RESET <= '0';
|
196 | FLASH_ENABLE <= '1';
|
197 | wait for 1000000 ns;
|
198 | FLASH_RESET <= '0';
|
199 | FLASH_ENABLE <= '0';
|
200 | wait for 1000000 ns;
|
201 | ---------------------
|
202 | FLASH_RESET <= '0';
|
203 | FLASH_ENABLE <= '1';
|
204 | wait for 1000000 ns;
|
205 | FLASH_RESET <= '0';
|
206 | FLASH_ENABLE <= '0';
|
207 | wait for 500000 ns;
|
208 | ---------------------
|
209 | FLASH_RESET <= '0';
|
210 | FLASH_ENABLE <= '1';
|
211 | wait for 1000000 ns;
|
212 | FLASH_RESET <= '0';
|
213 | FLASH_ENABLE <= '0';
|
214 | wait for 500000 ns;
|
215 | ---------------------
|
216 | FLASH_RESET <= '0';
|
217 | FLASH_ENABLE <= '1';
|
218 | wait for 1000000 ns;
|
219 | FLASH_RESET <= '0';
|
220 | FLASH_ENABLE <= '0';
|
221 | wait for 500000 ns;
|
222 | ---------------------
|
223 | FLASH_RESET <= '0';
|
224 | FLASH_ENABLE <= '1';
|
225 | wait for 1000000 ns;
|
226 | FLASH_RESET <= '0';
|
227 | FLASH_ENABLE <= '0';
|
228 | wait for 500000 ns;
|
229 | --------------------
|
230 | FLASH_RESET <= '0';
|
231 | FLASH_ENABLE <= '1';
|
232 | wait for 1000000 ns;
|
233 | FLASH_RESET <= '0';
|
234 | FLASH_ENABLE <= '0';
|
235 | wait for 800000 ns;
|
236 | FLASH_RESET <= '0';
|
237 | FLASH_ENABLE <= '1';
|
238 | wait for 500000 ns;
|
239 | --------------------
|
240 | FLASH_RESET <= '0';
|
241 | FLASH_ENABLE <= '0';
|
242 | wait for 800000 ns;
|
243 | FLASH_RESET <= '0';
|
244 | FLASH_ENABLE <= '1';
|
245 | wait;
|
246 | end process;
|
247 |
|
248 | END;
|