Moin,
ich versuche gerade zum ersten Mal, eine Schaltung mit XST direkt von
der Command Line zu synthetisieren. Das klappt leider nicht, weil XST
angeblich das Top Module nicht findet, obwohl es eigentlich da sein
müsste.
Das Modul selbst (MyTestModule.v):
1 | module MyTestModule (
|
2 | input x,
|
3 | output y
|
4 | );
|
5 |
|
6 | assign y = x;
|
7 |
|
8 | endmodule
|
XST-Projektdatei (test.prj):
1 | verilog work MyTestModule.v
|
XST-Skriptdatei (synthesize-xst-commands)
1 | run -arch spartan3 -p xc3s1000-ft256-4 -ifmt mixed -ifn test.prj -top MyTestModule -ofn test.ngc -ofmt NGC -work_lib work
|
Das ganze starte ich per
1 | xst -ifn synthesize-xst-commands
|
und bekomme folgende Ausgabe:
1 | Release 12.1 - xst M.53d (lin)
|
2 | Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
|
3 | -->
|
4 |
|
5 | TABLE OF CONTENTS
|
6 | 1) Synthesis Options Summary
|
7 | 2) HDL Compilation
|
8 | 3) Design Hierarchy Analysis
|
9 | 4) HDL Analysis
|
10 | 5) HDL Synthesis
|
11 | 5.1) HDL Synthesis Report
|
12 | 6) Advanced HDL Synthesis
|
13 | 6.1) Advanced HDL Synthesis Report
|
14 | 7) Low Level Synthesis
|
15 | 8) Partition Report
|
16 | 9) Final Report
|
17 | 9.1) Device utilization summary
|
18 | 9.2) Partition Resource Summary
|
19 | 9.3) TIMING REPORT
|
20 |
|
21 |
|
22 | =========================================================================
|
23 | * Synthesis Options Summary *
|
24 | =========================================================================
|
25 | ---- Source Parameters
|
26 | Input Format : mixed
|
27 | Input File Name : "test.prj"
|
28 |
|
29 | ---- Target Parameters
|
30 | Target Device : xc3s1000-ft256-4
|
31 | Output File Name : "test.ngc"
|
32 | Output Format : NGC
|
33 |
|
34 | ---- Source Options
|
35 | Architecture Name : spartan3
|
36 | Top Module Name : MyTestModule
|
37 | Work Library : work
|
38 |
|
39 | =========================================================================
|
40 |
|
41 | WARNING:Xst:29 - Optimization Effort not specified
|
42 | The following parameters have been added:
|
43 | Optimization Goal : SPEED
|
44 |
|
45 | =========================================================================
|
46 |
|
47 | =========================================================================
|
48 | * HDL Compilation *
|
49 | =========================================================================
|
50 | Compiling verilog file "MyTestModule.v" in library work
|
51 | Module <MyTestModule> compiled
|
52 | No errors in compilation
|
53 | Analysis of file <"test.prj"> succeeded.
|
54 |
|
55 | ERROR:Xst:2608 - Top module <MyTestModule> specified via the -top switch with architecture <spartan3> specified via the -arch switch was not found in the library <work> specified via -work_lib switch.
|
56 | -->
|
57 |
|
58 |
|
59 | Total memory usage is 134436 kilobytes
|
60 |
|
61 | Number of errors : 1 ( 0 filtered)
|
62 | Number of warnings : 1 ( 0 filtered)
|
63 | Number of infos : 0 ( 0 filtered)
|
Danke schonmal für jede Idee!