Hallo,
Ich wollte fragen, ob es so möglich ist ein >=32 Input <-> SPI
"Bridge" in VDHL zu realisieren.
Mein Anwendungsgebiet in dem Fall ist:
- 32 Tasten (nicht Matrix-Schaltung) an I/O Pins des Xilinx CPLD (95xx)
- SPI im Mode 0
- Atmel ATMega als SPI-Master mit SPI-Interrupts
Das ganze soll für ein Live-MIDI-Interface genutzt werden.
Da ich gerne die Ressourcen vom ATMega sparen wollte, habe
ich mir gedacht, dass ein CPLD als SPI-Slave vielleicht
eine Idee wert wäre. Nebenbei seih gesagt, dass ich noch
ein CPLD-Evaluationsboard rumliegen hätte, womit ich den
Testaufbau realisieren könnte.
spi32in.vhd:
1 | -- SPI-Slave for SPI Mode 0 --
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2 |
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3 | library IEEE;
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4 |
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5 | use IEEE.STD_LOGIC_1164.ALL;
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6 | use IEEE.NUMERIC_STD.ALL;
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7 |
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8 | entity SPI_Slave is
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9 | Generic (width: natural := 32);
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10 | Port(
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11 | SCLK : in STD_LOGIC;
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12 | SS : in STD_LOGIC;
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13 | MISO : out STD_LOGIC;
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14 | Din : in STD_LOGIC_VECTOR (width-1 downto 0)
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15 | );
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16 | end SPI_Slave;
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17 |
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18 | architecture Behavioral of SPI_Slave is
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19 | signal dinshr : STD_LOGIC_VECTOR (width-1 downto 0);
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20 |
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21 | begin
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22 | -- MISO - Master In Slave Out --
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23 |
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24 | process (SS, Din, SCLK)
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25 | begin
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26 | if(SS='1') then
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27 | dinshr <= Din;
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28 | elsif falling_edge(SCLK) then
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29 | dinshr <= dinshr(dinshr'left-1 downto 0) & '0';
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30 | end if;
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31 | end process;
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32 |
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33 | MISO <= dinshr(dinshr'left) when SS='0' else 'Z';
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34 | end Behavioral;
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spi32in.ucf für XL95144 TQFP100:
1 | NET "Din<0>" LOC = "P78" ;
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2 | NET "Din<10>" LOC = "P67" ;
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3 | NET "Din<11>" LOC = "P64" ;
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4 | NET "Din<12>" LOC = "P65" ;
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5 | NET "Din<13>" LOC = "P61" ;
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6 | NET "Din<14>" LOC = "P63" ;
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7 | NET "Din<15>" LOC = "P59" ;
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8 | NET "Din<16>" LOC = "P60" ;
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9 | NET "Din<17>" LOC = "P56" ;
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10 | NET "Din<18>" LOC = "P58" ;
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11 | NET "Din<19>" LOC = "P54" ;
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12 | NET "Din<1>" LOC = "P79" ;
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13 | NET "Din<20>" LOC = "P55" ;
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14 | NET "Din<21>" LOC = "P52" ;
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15 | NET "Din<22>" LOC = "P28" ;
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16 | NET "Din<23>" LOC = "P86" ;
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17 | NET "Din<24>" LOC = "P50" ;
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18 | NET "Din<25>" LOC = "P49" ;
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19 | NET "Din<26>" LOC = "P46" ;
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20 | NET "Din<27>" LOC = "P43" ;
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21 | NET "Din<28>" LOC = "P99" ;
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22 | NET "Din<29>" LOC = "P1" ;
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23 | NET "Din<2>" LOC = "P76" ;
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24 | NET "Din<30>" LOC = "P27" ;
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25 | NET "Din<31>" LOC = "P3" ;
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26 | NET "Din<3>" LOC = "P77" ;
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27 | NET "Din<4>" LOC = "P73" ;
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28 | NET "Din<5>" LOC = "P71" ;
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29 | NET "Din<6>" LOC = "P72" ;
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30 | NET "Din<7>" LOC = "P68" ;
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31 | NET "Din<8>" LOC = "P70" ;
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32 | NET "Din<9>" LOC = "P66" ;
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33 | NET "MISO" LOC = "P81" ;
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34 | NET "SCLK" LOC = "P82" ;
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35 | NET "SS" LOC = "P85" ;
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