Binärdatei in VHDL Testbench einlesen

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

entity tb_test is
end tb_test;

architecture Behavioral of tb_test is

COMPONENT test
    PORT (      data_in: in std_logic_vector( 7 downto 0);
        data_out: in std_logic_vector( 7 downto 0)
       );
end component;

  signal data_in,data_out :  std_logic_vector(7 DOWNTO 0);

begin

UUT: test PORT MAP(
  data_in => data_in,
  data_out => data_out
);


tb_data: process
type characterFile_Typ is file of character;
file f: characterFile_Typ open read_mode is "football.ts";
variable c:character;
begin
    -- init
    data_in<=x"00";
    while not endfile(f) loop
      Read( f=>f,
            value=>c);
     data_in <= CONV_STD_LOGIC_VECTOR(character'pos(c),8);
      wait for 10 ns;
    end loop;
    wait;
end process;
end;