1 | library UNISIM; -- für SRAM Template
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2 | use UNISIM.vcomponents.all; -- für SRAM Template
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3 | library ieee;
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4 | use ieee.std_logic_1164.all;
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5 | use ieee.std_logic_unsigned.all;
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6 |
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7 | entity RAM_4096x16 is
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8 | port (CLK, EN, RST, WE: in std_logic;
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9 | A: in std_logic_vector(11 downto 0);
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10 | DOUT: out std_logic_vector(15 downto 0);
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11 | DIN: in std_logic_vector(15 downto 0));
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12 | end RAM_4096x16;
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13 |
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14 | architecture Struktur of RAM_4096x16 is
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15 |
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16 | signal ENABLE: std_logic_vector(15 downto 0);
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17 | signal HADR: std_logic_vector(3 downto 0);
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18 | signal LADR: std_logic_vector(7 downto 0);
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19 |
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20 | begin
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21 |
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22 | HADR <= A(11 downto 8);
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23 | LADR <= A(7 downto 0);
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24 |
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25 | Decoder: process(HADR)
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26 | variable ENABLE_VAR: std_logic_vector(15 downto 0);
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27 | variable INT: integer range 0 to 15;
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28 | begin
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29 | ENABLE_VAR := (others => '0');
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30 | INT := conv_integer(HADR);
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31 | ENABLE_VAR(INT) := '1';
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32 | ENABLE <= ENABLE_VAR;
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33 | end process Decoder;
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34 |
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35 | -- <-----Cut code below this line and paste into the architecture
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36 | body---->
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37 |
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38 | -- RAMB4_S16: Virtex/E, Spartan-II/IIE 256 x 16 Single-Port RAM
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39 | -- Xilinx HDL Language Template version 7.1i
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40 |
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41 | GEN: for I in 15 downto 0 generate
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42 | RAMB4_S16_inst_01 : RAMB4_S16
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43 | generic map (
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44 | INIT_00 =>
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45 | X"0000000000000000000000000000000000000000000000000000000000000000",
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46 | INIT_01 =>
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47 | X"0000000000000000000000000000000000000000000000000000000000000000",
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48 | INIT_02 =>
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49 | X"0000000000000000000000000000000000000000000000000000000000000000",
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50 | INIT_03 =>
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51 | X"0000000000000000000000000000000000000000000000000000000000000000",
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52 | INIT_04 =>
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53 | X"0000000000000000000000000000000000000000000000000000000000000000",
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54 | INIT_05 =>
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55 | X"0000000000000000000000000000000000000000000000000000000000000000",
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56 | INIT_06 =>
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57 | X"0000000000000000000000000000000000000000000000000000000000000000",
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58 | INIT_07 =>
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59 | X"0000000000000000000000000000000000000000000000000000000000000000",
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60 | INIT_08 =>
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61 | X"0000000000000000000000000000000000000000000000000000000000000000",
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62 | INIT_09 =>
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63 | X"0000000000000000000000000000000000000000000000000000000000000000",
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64 | INIT_0A =>
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65 | X"0000000000000000000000000000000000000000000000000000000000000000",
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66 | INIT_0B =>
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67 | X"0000000000000000000000000000000000000000000000000000000000000000",
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68 | INIT_0C =>
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69 | X"0000000000000000000000000000000000000000000000000000000000000000",
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70 | INIT_0D =>
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71 | X"0000000000000000000000000000000000000000000000000000000000000000",
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72 | INIT_0E =>
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73 | X"0000000000000000000000000000000000000000000000000000000000000000",
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74 | INIT_0F =>
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75 | X"0000000000000000000000000000000000000000000000000000000000000000")
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76 | port map (
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77 | DO => DOUT, -- 16-bit data output
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78 | ADDR => LADR, -- 8-bit address input
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79 | CLK => CLK, -- Clock input
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80 | DI => DIN, -- 16-bit data input
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81 | EN => ENABLE(I), -- RAM enable input
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82 | RST => RST, -- Synchronous reset input
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83 | WE => WE -- RAM write enable input
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84 | );
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85 |
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86 | end generate;
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87 |
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88 | end Struktur;
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