1 | ----------------------------------------------------------------------------------
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2 | -- Company: www.kampis-elektroecke.de
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3 | -- Engineer: Daniel Kampert
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4 | --
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5 | -- Create Date: 02.08.2014 13:17:51
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6 | -- Design Name:
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7 | -- Module Name: VGA_Top - VGA_Top_Arch
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8 | -- Project Name:
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9 | -- Target Devices: XC7Z010CLG400-1
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10 | -- Tool Versions: Vivado 2014.2
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11 | -- Description: VGA Interface for a 640 x 480 Pixel Screen
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12 | --
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13 | -- Dependencies:
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14 | --
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15 | -- Revision:
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16 | -- Revision 0.01 - File Created
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17 | -- Additional Comments:
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18 | --
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19 | ----------------------------------------------------------------------------------
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20 |
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21 | library IEEE;
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22 | use IEEE.STD_LOGIC_1164.ALL;
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23 |
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24 | -- Uncomment the following library declaration if using
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25 | -- arithmetic functions with Signed or Unsigned values
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26 | use IEEE.NUMERIC_STD.ALL;
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27 |
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28 | -- Uncomment the following library declaration if instantiating
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29 | -- any Xilinx leaf cells in this code.
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30 | --library UNISIM;
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31 | --use UNISIM.VComponents.all;
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32 |
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33 | entity VGA_Top is
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34 | Port ( Color : out STD_LOGIC_VECTOR(15 downto 0);
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35 | HSync : out STD_LOGIC;
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36 | VSync : out STD_LOGIC;
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37 | Output : out STD_LOGIC_VECTOR(2 downto 0);
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38 | Reset : in STD_LOGIC;
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39 | Clock : in STD_LOGIC;
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40 | Button : in STD_LOGIC_VECTOR(3 downto 0)
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41 | );
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42 | end VGA_Top;
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43 |
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44 | architecture VGA_Top_Arch of VGA_Top is
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45 |
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46 | constant Char_Size : integer := 8;
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47 |
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48 | -- Clocksignale
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49 | signal Clock_VGA : std_logic;
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50 | signal Clock_1250 : std_logic;
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51 |
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52 | -- Koordinaten des Zeigers auf dem Bildschirm
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53 | signal Pos_x : std_logic_vector(9 downto 0) := "0001100100";
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54 | signal Pos_y : std_logic_vector(9 downto 0) := "0001100100";
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55 |
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56 | -- Font ROM
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57 | signal Character_No : std_logic_vector(1 downto 0);
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58 | signal Row_Addr : std_logic_vector(2 downto 0);
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59 | signal ROM_Col : std_logic_vector(2 downto 0);
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60 | signal ROM_Addr : std_logic_vector(4 downto 0);
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61 | signal ROM_Data : std_logic_vector(7 downto 0);
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62 | signal ROM_Bit : std_logic;
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63 |
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64 | -- Positionen
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65 | signal Pos_x_l : integer := 8;
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66 | signal Pos_y_t : integer := 8;
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67 | signal Pos_x_r : integer := Pos_x_l + Char_Size - 1;
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68 | signal Pos_y_b : integer := Pos_y_t + Char_Size - 1;
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69 |
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70 | -- Enable Signale für die Formen
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71 | signal Text_on : std_logic;
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72 |
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73 | -- Button
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74 | signal Button_Deb1 : std_logic;
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75 | signal Button_Deb2 : std_logic;
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76 | signal Button_Deb3 : std_logic;
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77 | signal Button_Deb4 : std_logic;
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78 |
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79 | signal Zaehler : integer;
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80 |
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81 | -- Systemsignale
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82 | signal Lock : std_logic;
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83 | signal Test : std_logic;
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84 |
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85 | -- Erzeugung des 25,175MHz Taktes
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86 | component System is
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87 | Port ( Clock_In : in STD_LOGIC;
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88 | Clock_Reset : in STD_LOGIC;
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89 | Clock_Locked : out STD_LOGIC;
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90 | Clock_Out : out STD_LOGIC
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91 | );
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92 | end component System;
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93 |
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94 | -- Einbinden des VGA-Controllers
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95 | component VGA_Controller is
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96 | Port ( HSync : out STD_LOGIC;
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97 | VSync : out STD_LOGIC;
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98 | Clock_VGA : in STD_LOGIC;
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99 | Reset : in STD_LOGIC;
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100 | x_out : out STD_LOGIC_VECTOR(9 downto 0);
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101 | y_out : out STD_LOGIC_VECTOR(9 downto 0)
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102 | );
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103 | end component VGA_Controller;
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104 |
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105 | component Clock_Div is
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106 | Port ( Clock_In : in STD_LOGIC;
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107 | Clock_Out : out STD_LOGIC;
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108 | Divider : in integer
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109 | );
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110 | end component Clock_Div;
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111 |
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112 | component Font_ROM is
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113 | Port ( Clock : in STD_LOGIC;
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114 | Adresse : in STD_LOGIC_VECTOR(4 downto 0);
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115 | Data : out STD_LOGIC_VECTOR(7 downto 0)
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116 | );
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117 | end component Font_ROM;
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118 |
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119 | component Debounce is
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120 | Port ( Input : in STD_LOGIC;
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121 | Output : out STD_LOGIC;
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122 | Clock : in STD_LOGIC;
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123 | Debouncetime : in integer
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124 | );
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125 | end component Debounce;
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126 |
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127 | begin
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128 |
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129 | Clock_25MHz : System port map (Clock, '1', Lock, Clock_VGA);
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130 | VGA_Core : VGA_Controller port map (HSync, VSync, Clock_VGA, Reset, Pos_x, Pos_y);
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131 | Clock_1k2Hz : Clock_Div port map (Clock_VGA, Clock_1250, 10000);
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132 | Font : Font_ROM port map (Clock_VGA, ROM_Addr, ROM_Data);
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133 |
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134 | Button_1 : Debounce port map (Button(0), Button_Deb1, Clock_1250, 50);
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135 | Button_2 : Debounce port map (Button(1), Button_Deb2, Clock_1250, 50);
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136 |
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137 | -- Wenn Position erreicht, Enable-Signal auf High setzen
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138 | Text_on <=
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139 | '1' when (Pos_x_l <= to_integer(unsigned(Pos_x))) and (to_integer(unsigned(Pos_x)) <= Pos_x_r) and
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140 | (Pos_y_t <= to_integer(unsigned(Pos_y))) and (to_integer(unsigned(Pos_y)) <= Pos_y_b) else '0';
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141 |
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142 | -- ROM auslesen
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143 | Row_Addr <= Pos_y(2 downto 0);
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144 | ROM_Addr <= Character_No & Row_Addr;
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145 |
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146 | ROM_Col <= Pos_x(2 downto 0);
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147 | ROM_Bit <= ROM_Data(to_integer(unsigned(ROM_Col)));
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148 |
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149 | Character_No <= std_logic_vector(to_unsigned(Zaehler, Character_No'length));
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150 |
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151 | process(Button_Deb1)
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152 | begin
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153 | if(rising_edge(Button_Deb1)) then
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154 | Zaehler <= Zaehler + 1;
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155 | end if;
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156 | end process;
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157 |
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158 | -- Formen am Bildschirm ausgeben
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159 | process(Clock_VGA)
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160 | begin
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161 | if(rising_edge(Clock_VGA)) then
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162 |
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163 | Color <= x"0000";
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164 |
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165 | if((ROM_Bit = '1') and (Text_on = '1')) then
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166 | Color <= x"FC00";
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167 | end if;
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168 |
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169 | end if;
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170 | end process;
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171 |
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172 | -- Betriebsstatus
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173 | Output(2) <= Button_Deb1;
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174 | Output(1) <= Lock;
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175 | Output(0) <= Reset;
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176 |
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177 | end VGA_Top_Arch;
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